Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

1. A method comprising:

providing a semiconductor structure comprising a substrate and a plurality of layers above the substrate;

carrying out a first lithography and etch to form a first intermediate semiconductor structure comprising a first set of surface features;

forming one or more additional layers covering the first intermediate semiconductor structure;

carrying out a second lithography and etch to form a second intermediate semiconductor structure comprising a second set of surface features adjacent the first set of surface features;

carrying out a third etch to form a first set of mandrels corresponding to the first set of surface features and a second set of mandrels corresponding to the second set of surface features;

forming sidewall spacers on the first and second sets of mandrels;

removing the first and second sets of mandrels to form a third intermediate semiconductor structure; and

carrying out a fourth etch to form a fourth intermediate semiconductor structure in which a pattern formed by the sidewall spacers is transferred to one of the layers above the substrate.

2. The method of claim 1 , wherein the plurality of layers above the substrate comprise hardmask layers and other pattern-transfer layers comprising dielectric layers, amorphous-silicon layers, amorphous-carbon layers, titanium oxide layers, and/or organic planarization layers.

3. The method of claim 1 , wherein the fourth etch forms the pattern in an amorphous-silicon layer.

4. The method of claim 1 , wherein the fourth etch forms the pattern in an amorphous-carbon layer.

5. The method of claim 1 , further comprising:

carrying out a fifth etch to form fins in the substrate corresponding to the pattern.

6. The method of claim 1 , wherein the first and second sets of surface features are interleaved and a center-to-center distance of first and second surface features of the first set of surface features is different than a center-to-center distance of first and second surface features of the second set of surface features.

7. The method of claim 1 , wherein the first and second sets of surface features are interleaved and a center-to-center distance of first and second surface features of the first set of surface features is the same as a center-to-center distance of first and second surface features of the second set of surface features.

8. The method of claim 1 , wherein the first and second sets of surface features are not interleaved and a center-to-center distance of first and second surface features of the first set of surface features is different than a center-to-center distance of first and second surface features of the second set of surface features.

9. The method of claim 1 , wherein the first and second sets of surface features are not interleaved and a center-to-center distance of first and second surface features of the first set of surface features is the same as a center-to-center distance of first and second surface features of the second set of surface features.

10. The method of claim 1 , wherein a final pattern is formed without a second sidewall spacer formation.

11. The method of claim 6 , wherein a center-to-center difference between the first surface feature of the first set of surface features and the first surface feature of the second set of surface features is less than half the center-to-center distance of first and second surface features of the first set of surface features.

12. The method of claim 7 , wherein a center-to-center difference between the first surface feature of the first set of surface features and the first surface feature of the second set of surface features is less than half the center-to-center distance of first and second surface features of the second set of surface features.

13. The method of claim 12 , wherein:

first and second sidewall spacer pattern features correspond to sidewall spacers of a mandrel of the first set of mandrels corresponding to the first surface feature of the first set of surface features;

third and fourth sidewall spacer pattern features correspond to sidewall spacers of a mandrel of the second set of mandrels corresponding to the first surface feature of the second set of surface features;

fifth and sixth sidewall spacer pattern features correspond to sidewall spacers of a mandrel of the first set of mandrels corresponding to the second surface feature of the first set of surface features;

seventh and eighth sidewall spacer pattern features correspond to sidewall spacers of a mandrel of the second set of mandrels corresponding to the second surface feature of the second set of surface features;

(i) a distance between the first and second sidewall spacer pattern features, (ii) a distance between the third and fourth sidewall spacer pattern features, (iii) a distance between the fifth and sixth sidewall spacer pattern features, and (iv) a distance between the seventh and eighth sidewall spacer pattern features are all less than a distance between the second and third sidewall spacer pattern features and a distance between the sixth and seventh sidewall spacer pattern features, which are both less than a distance between the fourth and fifth sidewall spacer pattern features; and

the first, second, third, fourth, fifth, sixth, seventh, and eighth sidewall spacer pattern features are formed without (i) a second sidewall spacer formation and (ii) an additional etch to remove one or more sidewall spacer pattern features.

14. A method comprising:

providing a semiconductor structure comprising a substrate and a plurality of layers above the substrate;

carrying out a first lithography and etch to form a first intermediate semiconductor structure comprising a first set of surface features;

forming one or more additional layers covering the first intermediate semiconductor structure;

carrying out a second lithography and etch to form a second intermediate semiconductor structure comprising a second set of surface features adjacent to the first set of surface features, wherein the first set of surface features have a first pitch, and wherein the second set of surface features have a second pitch different than the first pitch;

carrying out a third etch to form a first set of mandrels corresponding to the first set of surface features and a second set of mandrels corresponding to the second set of surface features;

forming sidewall spacers on the first and second sets of mandrels;

removing the first and second sets of mandrels to form a third intermediate semiconductor structure; and

carrying out a fourth etch to form a fourth intermediate semiconductor structure in which a pattern formed by the sidewall spacers is transferred to one of the layers above the substrate.

15. The method of claim 14 , wherein the second set of surface features are adjusted with respect to the first set of surface features by less than half the first pitch to provide a surface structure-free region.

16. The method of claim 14 , wherein the plurality of layers above the substrate comprise hardmask layers and other pattern-transfer layers comprising dielectric layers, amorphous-silicon layers, amorphous-carbon layers, titanium oxide layers, and/or organic planarization layers.

17. The method of claim 16 , wherein the fourth etch forms the pattern in an amorphous-silicon layer.

18. The method of claim 14 , wherein the fourth etch forms the pattern in an amorphous-carbon layer.

19. The method of claim 14 , further comprising:

carrying out a fifth etch to form fins in the substrate corresponding to the pattern.

20. The method of claim 14 , wherein a final pattern is formed without a second sidewall spacer formation.