Nanosheet channel-to-source and drain isolation
View Patent ↗A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
1. A structure used to fabricate a nanosheet semiconductor device, the structure comprising:
a substrate;
two or more sets of silicon layers formed above the substrate, wherein each of the two or more sets of silicon layers is parallel to others of the two or more sets of silicon layers in a first direction and each of the two or more sets of silicon layers includes gaps between adjacent ones of the silicon layers of each respective set of silicon layers; and
a dielectric material configured to anchor each of the two or more sets of silicon layers at a first end and a second end of each of the two or more sets of silicon layer along a second direction, which is perpendicular to the first direction, wherein the dielectric material partially fills the gaps between the adjacent ones of the silicon layers of each respective set of silicon layers of the two or more sets of silicon layers and is between adjacent ones of the two or more sets of silicon layers.
2. The structure according to claim 1 , wherein the dielectric material is silicon nitride.
3. The structure according to claim 1 , further comprising an oxide filling the gaps between the adjacent ones of the silicon layers of each respective set of silicon layers of the two or more sets of silicon layers that are unfilled by the dielectric material.
4. The structure according to claim 1 , further comprising a dummy gate stack formed above one of the two or more sets of silicon layers.
5. The structure according to claim 4 , further comprising a gate oxide between the one of the two or more sets of silicon layers and the dummy gate stack.
6. The structure according to claim 4 , wherein the dummy gate stack includes a dummy gate.
7. The structure according to claim 4 , wherein the dummy gate stack includes a gate hardmask.
8. The structure according to claim 4 , wherein the dummy gate stack includes a gate oxide hardmask.
9. The structure according to claim 4 , further comprising low-k dielectric spacers on each side of the dummy gate stack.