Fabrication of a vertical fin field effect transistor with reduced dimensional variations

1. A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, comprising:

forming two dummy fin trenches in a substrate, wherein each of the two dummy fin trenches is on opposite sides of a portion of the substrate;

forming a dummy fin fill in each of the two dummy fin trenches;

forming a first dummy fin from one of the dummy fin fills, a second dummy fin from the other of the two dummy fin fills, and a vertical fin from the portion of the substrate between the two dummy fin trenches, wherein the first dummy fin and second dummy fin are border fins and the vertical fin is an interior fin; and

removing the border fins.

2. The method of claim 1 , wherein the border fins and interior fin have a width in the range of about 4 nm to about 20 nm.

3. The method of claim 1 , wherein the dummy fin fill and the border fins are made of amorphous silicon (a-Si), poly-crystalline silicon (p-Si), amorphous silicon-germanium (a-SiGe), or poly-crystalline silicon-germanium (p-SiGe).

4. The method of claim 3 , wherein the vertical fin is single crystal silicon, and the border fins are removed by a selective HCl etch.

5. The method of claim 1 , wherein the width of each of the two dummy fin trenches is in the range of about 30 nm to about 300 nm.

6. The method of claim 5 , wherein the depth of each of the two dummy fin trenches is in the range of 20 nm to about 200 nm.

7. The method of claim 6 , further comprising forming a doped region in the portion of the substrate.

8. The method of claim 7 , further comprising forming a gate structure on the vertical fin.

9. The method of claim 8 , forming a punch-through stop in a lower portion of the vertical fin.

10. The method of claim 9 , further comprising forming a top source/drain on the vertical fin.