SRAM design to facilitate single fin cut in double sidewall image transfer process
View Patent ↗A double sidewall image transfer process for forming FinFET structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by the width of a sidewall spacer that forms a second mandrel. Here, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space between paired fins is created by placing two first mandrel shapes close enough so as to overlap or merge two sidewall spacer shapes so as to form a wider second mandrel upon further processing. The fin pair created from the wider second mandrel is spaced at about 2 times the fin pair created from the narrower second mandrel. For some circuits, such as an SRAM bitcell, the wider second mandrel can be utilized to form an inactive fin not utilized in the circuit structure, which can be removed. In some embodiments, all dummy inactive fins are eliminated for a simpler process.
1. A process for forming a fin structure having a fin pitch of less than 40 nanometers, the process comprising:
providing a multilayer structure overlaying a semiconductor substrate, wherein the multilayer structure comprises a planar cap layer, and alternating dielectric and hard mask layers stackedly arranged on the semiconductor substrate;
lithographically patterning a photoresist disposed on the cap layer to form a first mandrel pattern consisting of first and second mandrel shapes;
forming first sidewall spacers on the first mandrel pattern, wherein sidewall spacers between adjacent first and second mandrel shapes overlap or merge;
removing the first mandrel pattern and etching the structure to form a second mandrel pattern consisting of a first mandrel shape and a second mandrel shape, wherein the second mandrel shape is at about two times a width of the first mandrel shape;
forming second sidewall spacers on the second mandrel pattern; and
etching the structure to form multiple fin pairs in the semiconductor substrate comprising fin pairs having a minimal spacing and fin pairs that are about two times the minimal spacing.
2. The process of claim 1 , further comprising removing one of the fins in the fin pair at about two times the minimal spacing, wherein the removed fin is an inactive fin.
3. The process of claim 1 , wherein forming the first and second sidewall spacers comprises a conformally depositing a spacer layer on the respective first and second mandrel pattern and anisotropically etching the substrate.
4. The process of claim 3 , wherein anisotropically etching the substrate comprises a reactive ion etch process.
5. The process of claim 1 , wherein the removed fin defines an isolation region between adjacent active regions of a device.
6. The process of claim 1 , wherein the first and second mandrel patterns are formed of amorphous silica.
7. The process of claim 1 , wherein the semiconductor substrate comprises a bulk semiconductor substrate or a semiconductor-on-insulator substrate.
8. The process of claim 1 , wherein the cap layer is an organic planarization layer (OPL) or a planar anti-reflective coating (ARC).
9. The process of claim 1 , further comprising removing one of the fins in the fin pair at about two times the minimal spacing, wherein the removed fin is an inactive fin.
10. The process of claim 1 , wherein forming the first and second sidewall spacers comprises a conformally depositing a spacer layer on the respective first and second mandrel pattern and anisotropically etching the substrate.
11. The process of claim 1 , wherein the removed fin defines an isolation region between adjacent active regions of a device.
12. The process of claim 1 , wherein the first and second mandrel patterns are formed of amorphous silica.
13. A process for forming a fin structure having a fin pitch of less than 40 nanometers, the process comprising:
providing a multilayer structure overlaying a semiconductor substrate, wherein the multilayer structure comprises a planar cap layer, and alternating dielectric and hard mask layers stackedly arranged on the semiconductor substrate;
lithographically patterning a photoresist disposed on the cap layer to form a first mandrel pattern consisting of first and second mandrel shapes;
forming first sidewall spacers on the first mandrel pattern, wherein sidewall spacers between adjacent first and second mandrel shapes define a small gap therebetween, wherein the small gap is a sub-threshold assist feature;
removing the first mandrel pattern and etching the structure to form a second mandrel pattern consisting of a first mandrel shape and a second mandrel shape, wherein the second mandrel shape is at about two times a width of the first mandrel shape, and wherein the second mandrel shape is free of the sub-threshold assist feature;
forming second sidewall spacers on the second mandrel pattern; and
etching the structure to form multiple fin pairs in the semiconductor substrate comprising fin pairs have a minimal spacing and fin pairs are about two time the minimal spacing.
14. The process of claim 13 , wherein anisotropically etching the substrate comprises a reactive ion etch process.