Nanosheet channel-to-source and drain isolation
View Patent ↗A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
1. A method of fabricating a semiconductor device, the method comprising:
providing first and second nanosheet fins, wherein each of the first nanosheet fin and the second nanosheet fin comprises at least two first layers and at least two second layers disposed on a substrate, wherein the at least two first layers are arranged alternatingly with the at least two second layers, wherein the first and second nanosheet fins are adjacent and in-line, and wherein the first and second nanosheet fins are separated by a trench filled with a trench-dielectric;
depositing a dummy gate-dielectric layer over the first and second nanosheet fins and the trench-dielectric;
forming a dummy gate stack and sidewall spacers over a portion of the first nanosheet fin;
etching the first nanosheet fin using the dummy gate stack and sidewall spacers as an etch-mask to expose sidewalls of the at least two first layers and the at least two second layers,
recessing the sidewalls of the at least two second layers with respect to sidewalls of the at least two first layers to form divots;
filling the divots to form inner spacers;
epitaxially growing a source-drain region contacting exposed sidewalls of the at least two first layers and remaining trench-dielectric;
removing the dummy gate stack to leave an opening between the sidewall spacers;
selectively removing the at least two second layers and the dummy gate-dielectric layer;
depositing a high-k gate dielectric layer and a work-function metal layer on and between the exposed portions of the at least two first layers; and
depositing a gate metal on exposed portions of the work-function metal layer.
2. The method of claim 1 , wherein each of the at least two first layers comprise a semiconductor layer.
3. The method of claim 1 , wherein each of the at least two first layers comprise a silicon layer.
4. The method of claim 1 , wherein each of the at least two second layers comprise a dielectric layer.
5. The method of claim 1 , wherein each of the at least two second layers comprise an oxide layer.
6. The method of claim 1 , wherein the dummy gate stack is formed on top of the dummy gate-dielectric layer.
7. The method of claim 1 , wherein etching the at least two first layers and the at least two second layers of the nanosheet fin is performed selectively with respect to the trench-dielectric.
8. The method of claim 1 , wherein recessing exposed sidewalls of the at least two second layers is performed with an anisotropic etch.
9. The method of claim 1 , wherein depositing the high-k gate dielectric and work-function metal layers further comprises depositing the high-k gate dielectric and work-function metal layers on inner walls of the sidewall spacers.
10. The method of claim 9 , further comprising:
filling a remaining gap in the gate with a gate-metal; and
performing a CMP process to remove excess gate-metal material.
11. The method of claim 1 , wherein the inner spacers comprise SiN.