IP Library Granted Patent US 10,224,247
Granted Patent B2
US 10,224,247 · App. 16/115,953 · Granted Mar 5, 2019

FinFET devices

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Quick Facts
Patent No.
US 10,224,247
App. No.
16/115,953
Granted
Mar 5, 2019
Kind
B2
Abstract

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Claims (33)

1. A method of forming a semiconductor structure, the method comprising:

forming a plurality of fin structures which are supported by insulator material at a bottom portion thereof, such that the fin structures are partially exposed, wherein:

the insulator material is a high-density-plasma oxide between first facing sides of the fin structures and another insulator material between second facing sides of the fin structures, which are on other sides of the fin structures with respect to the first facing sides,

the high-density-plasma oxide contacts vertical portions of sidewalls of the first facing sides of the fin structures,

the other insulator material contacts vertical portions of sidewalls of the second facing sides of the fin structures, and

the another insulating material is an annealed flowable oxide.

2. The method of claim 1 , wherein the plurality of fin structures are supported by the insulator material at opposing sides of the bottom portion thereof.

3. The method of claim 1 , wherein the plurality of fin structures are substrate material.

4. The method of claim 3 , wherein the plurality of fin structures are supported by the insulator material on opposing sides thereof.

5. The method of claim 3 , wherein the insulator material is recessed compared to the plurality of fin structures.

6. The method of claim 1 , wherein the vertical portions of the sidewalls of the first facing sides of the fin structures are parallel to one another.

7. The method of claim 1 , wherein the vertical portions of the sidewalls of the first facing sides of the fin structures are non-sloping.

8. The method of claim 1 , wherein the high-density-plasma oxide has a rectangular shape between the vertical portions of the sidewalls of the first facing sides of the fin structures.

9. A method of forming a semiconductor structure, the method comprising:

forming a plurality of fin structures which are supported by insulator material at opposing sides of a bottom portion thereof, such that the fin structures are partially exposed, wherein:

the plurality of fin structures are substrate material,

the insulator material is recessed compared to the plurality of fin structures,

the insulator material is an annealed flowable oxide between first facing sides of the fin structures and another insulator material between second facing sides of the fin structures, which are on other sides of the fin structures with respect to the first facing sides,

the annealed flowable oxide contacts vertical portions of sidewalls of the first facing sides of the fin structures, and the other insulator material contacts vertical portions of sidewalls of the second facing sides of the fin structures,

the another insulating material is different than the annealed flowable oxide.

10. The method of claim 9 , wherein the another insulating material is high-density-plasma oxide.

11. The method of claim 9 , wherein the vertical portions of the sidewalls of the first facing sides of the fin structures are parallel to one another.

12. The method of claim 9 , wherein the vertical portions of the sidewalls of the first facing sides of the fin structures are non-sloping.

13. The method of claim 9 , wherein the annealed flowable oxide has a rectangular shape between the vertical portions of the sidewalls of the first facing sides of the fin structures.

14. A method of forming a semiconductor structure, the method comprising:

forming a plurality of fin structures which are supported by insulator material at opposing sides of a bottom portion thereof, such that the fin structures are partially exposed, wherein:

the plurality of fin structures are substrate material,

the insulator material is recessed compared to the plurality of fin structures,

the insulator material is a first insulator material between first facing sides of the fin structures and a second insulator material between second facing sides of the fin structures, which are on other sides of the fin structures with respect to the first facing sides, the second insulator material being a different material than the first insulator material, and

the first insulator material and the second insulator material contact vertical portions of sidewalls of opposite sides of respective ones of the plurality of fin structures.

15. The method of claim 14 , wherein the first insulator material and the second insulator material are in trenches of substantially equal depth on opposite sides of respective ones of the plurality of fin structures.

16. The method of claim 14 , wherein the first insulator material and the second insulator material are different types of oxide material.

17. The method of claim 14 , wherein the first insulator material is annealed flowable oxide and the second insulator material is high-density-plasma oxide.

Assignments (5)
CHANGE OF NAME Recorded Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0410 →
CERTIFICATE OF CONVERSION & CHANGE OF NAME Recorded Sep 7, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 061388/0199 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2018
From: BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; STANDAERT, THEODORUS E.; WANG, JUNLI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 046741/0430 →
Cited By (1)
US 12,376,369