Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
View Patent ↗Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.
1. A field effect transistor (FinFET) device, comprising:
a semiconductor substrate layer;
a dielectric layer on the semiconductor substrate layer;
crystalline fin portions separate from the semiconductor substrate layer and located within the dielectric layer, the fin portions having a surface oriented in a crystalline plane and being located in source/drain regions of the device, the fin portions being dielectrically isolated from each other by the dielectric layer;
an epitaxial layer of semiconductor material formed on the crystalline fin portions in the source/drain regions, wherein the surface of the fins provides a seed surface for forming the epitaxial layer; and
a gate structure located between the source/drain regions.
2. The device of claim 1 , wherein the semiconductor substrate layer is comprised of a material selected from silicon, germanium, and silicon germanium.
3. The device of claim 2 , wherein the fin portions are formed from the semiconductor substrate layer.
4. The device of claim 1 , wherein the fin portions are formed from the semiconductor substrate layer.
5. The device of claim 1 , wherein the seed surfaces of the crystalline fin portions are oriented in the {100} lattice plane.
6. The device of claim 1 , wherein the epitaxial layer is comprised of a material selected from silicon, germanium and silicon germanium.
7. The device of claim 1 , wherein the fin portions are crystalline silicon, the seed surfaces of which are oriented in {100} lattice plane, and the epitaxial layer is silicon germanium.
8. The device of claim 1 , wherein the gate structure is comprised of a gate conductor comprising a material selected from titanium nitride, ruthenium, titanium aluminum, aluminum nitride, and tantalum carbide.
9. The device of claim 1 , further comprising a high dielectric constant material provided around the gate conductor.
10. The device of claim 1 , further comprising trenches etched in the semiconductor substrate layer to isolate individual FinFET devices.