Fabrication of a vertical fin field effect transistor with reduced dimensional variations
View Patent ↗A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
1. A fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, comprising:
a plurality of vertical fins within a perimeter of a fin pattern region on a substrate;
a step formed in the substrate surrounding the plurality of vertical fins;
a doped region within the perimeter of the fin pattern region below the plurality of vertical fins, wherein the depth of the doped region is less than the height of the step;
a dielectric layer on the step and at least a portion of the plurality of vertical fins; and
a gate dielectric layer on at least a portion of the sidewalls of the plurality of vertical fins and on the dielectric layer, wherein the gate dielectric layer extends over at least a portion of the step.
2. The finFET of claim 1 , wherein the step has a height in the range of about 5 nm to about 50 nm.
3. The finFET of claim 2 , further comprising a gate electrode layer on the gate dielectric layer, wherein the gated length of the vertical fins is in the range of about 10 nm to about 50 nm.
4. The finFET of claim 3 , further comprising a top spacer formed on the gate electrode layer.
5. The finFET of claim 1 , further comprising a top source/drain on the top portion of each of the plurality of vertical fins.
6. The finFET of claim 1 , further comprising a punch-through stop in a lower portion of each of the plurality of vertical fins.
7. A fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, comprising:
a plurality of vertical fins within a perimeter of a fin pattern region on a substrate;
a step formed in the substrate around the plurality of vertical fins;
a ledge adjoining at least one of the plurality of vertical fins, where the ledge is between the step and the at least one of the plurality of vertical fins;
a doped region within the perimeter of the fin pattern region below the plurality of vertical fins, wherein the depth of the doped region is less than the height of the step;
a dielectric layer on the step, the ledge, and at least a portion of each of the plurality of vertical fins; and
a doped region within the perimeter of the fin pattern region below the plurality of vertical fins, wherein the depth of the doped region is less than the height of the step.
8. The finFET of claim 7 , wherein each of the plurality of vertical fins are electrically coupled to the same doped region.
9. The finFET of claim 8 , further comprising a top source/drain on the top portion of each of the plurality of vertical fins.
10. The finFET of claim 9 , wherein the top source/drains are electrically coupled to form a multi-fin FinFET.
11. The finFET of claim 10 , further comprising a gate structure on a central portion of the plurality of vertical fins.
12. The finFET of claim 11 , wherein the gate structure has a gate length in the range of about 10 nm to about 50 nm.
13. The finFET of claim 10 , further comprising a top spacer on the gate structure, wherein the top spacer is silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
14. A fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, comprising:
one or more vertical fins on a raised region of a substrate, wherein the raised region includes a step formed in the substrate around the one or more vertical fins and a ledge adjacent to at least one of the one or more vertical fins, where the ledge is between the step and the at least one of the one or more of vertical fins; and
a doped region in the raised region of the substrate, wherein the raised region forms a bottom source/drain below the one or more vertical fins, and the thickness of the bottom source/drain is less than the height of the step.
15. The finFET of claim 14 , wherein the one or more vertical fins have a width in the range of about 4 nm to about 20 nm.
16. The finFET of claim 14 , wherein the doped region is n-doped.
17. The finFET of claim 14 , wherein the step has a height in the range of about 5 nm to about 50 nm.
18. The finFET of claim 14 , further comprising a gate structure on the one or more vertical fins, wherein the gate structure has a gate length in the range of about 10 nm to about 50 nm.