Nanowire with sacrificial top wire
View Patent ↗Field effect transistors and methods of forming the same include forming a stack of nanowires of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
1. A method for forming a field effect transistor, comprising:
forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack;
forming a dummy gate over the stack;
etching away the channel material and the sacrificial material of the stack of nanowires outside of a region covered by the dummy gate, then
selectively etching the sacrificial material to form recesses in the sacrificial material layers;
forming spacers in the recesses in the sacrificial material layers, with at least one pair of spacers being formed in recesses above an uppermost layer of the channel material;
etching away the dummy gates with an anisotropic etch, where the top layer of the sacrificial material protects the uppermost layer of the channel material from damage from the anisotropic etch;
etching away the sacrificial material to expose the layers of the channel material; and
forming a gate stack over and around the layers of the channel material.
2. The method of claim 1 , further comprising forming merged source and drain regions at respective ends of the layers of the channel material.
3. The method of claim 2 , wherein the merged source and drain regions cover the spacers in the recesses in the sacrificial material layers.
4. The method of claim 2 , wherein forming the merged source and drain regions comprises epitaxially growing the source and drain regions from exposed faces of the layers of the channel material.
5. The method of claim 1 , wherein the spacers each have a crescent shape.
6. The method of claim 1 , wherein forming the spacers in the recesses in the sacrificial material layers comprises conformally depositing spacer material and etching away the spacer material outside of the recesses.
7. The method of claim 1 , further comprising: forming an initial spacer on sidewalls of the dummy gate before etching the channel material and the sacrificial material of the stack of nanowires, such that the channel material and the sacrificial material of the stack of nanowires directly under the spacers is not removed; and etching away the initial spacer before forming the spacers in the recesses of the sacrificial material.
8. The method of claim 1 , further comprising forming lateral dummy gates on each side of the dummy gate.
9. The method of claim 8 , wherein etching the channel material and the sacrificial material of the stack of nanowires etches away only the channel material and the sacrificial material of the stack of nanowires not covered by the dummy gate and the lateral dummy gates.
10. The method of claim 8 , further comprising forming vestigial source and drain regions at ends of the layers of the channel material in regions covered by the lateral dummy gates.
11. The method of claim 1 , wherein the nanowires each has a cross-sectional width that is less than twice a cross-sectional height.
12. A method for forming a field effect transistor, comprising:
forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack;
forming a dummy gate over the stack;
forming an initial spacer on sidewalls of the dummy gate;
etching away the channel material and the sacrificial material of the stack of nanowires outside of a region covered by the dummy gate and the initial spacer, then
selectively etching the sacrificial material to form recesses in the sacrificial material layers;
etching away the initial spacer;
forming crescent-shaped spacers in the recesses in the sacrificial material layers, with at least one pair of spacers being formed in recesses above an uppermost layer of the channel material;
forming merged source and drain regions at respective ends of the layers of the channel material, said merged source and drain regions covering the spacers in the recesses in the sacrificial material layers;
etching away the dummy gates with an anisotropic etch, where the top layer of the sacrificial material protects the uppermost layer of the channel material from damage from the anisotropic etch;
etching away the sacrificial material to expose the layers of the channel material; and forming a gate stack over, around, and between the layers of the channel material.
13. The method of claim 12 , wherein forming the crescent-shaped spacers in the recesses in the sacrificial material layers comprises conformally depositing spacer material and etching away the spacer material outside of the recesses.
14. The method of claim 12 , further comprising: forming lateral dummy gates on each side of the dummy gate; and forming vestigial source and drain regions at ends of the layers of the channel material in regions covered by the lateral dummy gates.