Transistor with improved air spacer
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.
1. A semiconductor structure comprising at least:
a gate stack disposed on a substrate;
a gate contact disposed in contact with an end portion of the gate stack and extending over an active area of the semiconductor structure; and
an air gap spacer comprising an insulating material disposed in contact with a portion of the gate stack and further comprising at least three separate air gaps surrounded by the insulating material on corresponding sides of the gate stack, wherein the end portion of the one gate stack is absent the air gap spacer.
2. The semiconductor structure of claim 1 , wherein the air gap spacer comprises a plurality of air gaps surrounded by an insulating material.
3. The semiconductor structure of claim 1 , wherein the gate contact wraps around the end portion of the gate stack.
4. The semiconductor structure of claim 1 , wherein the gate contact is in contact with
a portion of a top surface of a gate,
sidewalls of the gate, and
sidewalls of a dielectric layer under and in contact with the gate.
5. The semiconductor structure of claim 1 , further comprising:
a cap layer in contact with a portion of the top surface of the gate stack.
6. The semiconductor structure of claim 1 , further comprising:
a source contact disposed in contact with a portion of a source region of the substrate and the air gap spacer; and
a drain contact disposed in contact with a portion of a drain region of the substrate and the air gap spacer.
7. The semiconductor structure of claim 6 , further comprising:
a dielectric layer in contact with at least the source contact, drain contact, and gate contact.
8. An integrated circuit comprising:
a semiconductor device, wherein the semiconductor device comprises at least:
a gate stack disposed on a substrate;
a gate contact disposed in contact with an end portion of the gate stack and extending over an active area of the semiconductor structure; and
an air gap spacer comprising an insulating material disposed in contact with a portion of the gate stack and further comprising at least three separate air gaps surrounded by the insulating material on corresponding sides of the gate stack, wherein the end portion of the one gate stack is absent the air gap spacer.
9. The integrated circuit of claim 8 , wherein the air gap spacer comprises a plurality of air gaps surrounded by an insulating material.
10. The integrated circuit of claim 8 , wherein the gate contact wraps around the end portion of the gate stack.
11. The integrated circuit of claim 8 , wherein the gate contact is in contact with
a portion of a top surface of a gate,
sidewalls of the gate, and
sidewalls of a dielectric layer under and in contact with the gate.
12. The integrated circuit of claim 8 , wherein the semiconductor device further comprises:
a cap layer in contact with a portion of the top surface of the gate stack.
13. The integrated circuit of claim 8 , wherein the semiconductor device further comprises:
a source contact disposed in contact with a portion of a source region of the substrate and the air gap spacer; and
a drain contact disposed in contact with a portion of a drain region of the substrate and the air gap spacer.
14. The semiconductor structure of claim 13 , further comprising:
a dielectric layer in contact with at least the source contact, drain contact, and gate contact.
15. A semiconductor structure comprising at least:
a plurality of gate stacks disposed on a substrate;
a plurality of gate contacts, wherein each gate contact in the plurality of gate contacts is disposed in contact with an end portion of one gate stack of the plurality of gate stacks; and
a plurality of air gap spacers, wherein each air gap spacer of the plurality of air spacers comprises an insulating material disposed in contact with a portion of the one gate stack and further comprises at least three separate air gaps surrounded by the insulating material on corresponding sides of the one gate stack, wherein the end portion of the one gate stack is absent the air gap spacer.
16. The semiconductor structure of claim 15 , wherein each air gap spacer of the plurality of air gap spacers comprises a plurality of air gaps surrounded by an insulating material.
17. The semiconductor structure of claim 15 , wherein each gate contact of the plurality of gate contacts wraps around the end portion of the one gate stack.
18. The semiconductor structure of claim 15 , wherein each gate contact of the plurality of gate contacts is in contact with
a portion of a top surface of a gate,
sidewalls of the gate, and
sidewalls of a dielectric layer under and in contact with the gate.
19. The semiconductor structure of claim 15 , further comprising:
a plurality of cap layers, wherein each cap layer of the plurality of cap layers is in contact with a portion of a top surface of one gate stack of the plurality of gate stacks.
20. The semiconductor structure of claim 15 , further comprising:
a plurality of source contacts, wherein each source contact of the plurality of source contacts is disposed in contact with a portion of a source region of the substrate and one air gap spacer in the plurality of air gap spacers; and
a plurality of drain contacts, wherein each drain contact in the plurality of drain contacts is disposed in contact with a portion of a drain region of the substrate and one air gap spacer in the plurality of air gap spacers.