Forming insulator fin structure in isolation region to support gate structures

1. A method for forming a semiconductor device comprising:

forming a plurality of fin structures across a semiconductor substrate including active regions and isolation regions;

forming a hardmask dielectric on the semiconductor substrate contacting the fin structure sidewalls, wherein an upper surface of the plurality of fin structures is exposed;

removing portions of the plurality of fin structures present on the isolation regions of the substrate to form fin trenches having sidewalls defined by the hardmask dielectric, wherein portions of the fin structures present on the active regions of the substrate remain;

forming a dielectric fin in the fin trenches adjacent to the portion of the fin structures present on the active regions of the substrate; and

forming gate structures on the channel region of the fin structures present on the active regions of the substrate and the dielectric fin on the isolation regions.

2. The method of claim 1 further comprising forming epitaxial source and drain regions on source and drain portions of the fin structures present on the active regions, wherein the dielectric fin structures support the gate structure over the isolation regions.

3. The method of claim 1 , wherein the plurality of fin structures are comprised of a semiconductor material selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with carbon (Si:C), type III-V semiconductors and combinations thereof.

4. The method of claim 1 , wherein the forming of said plurality of fin structures across the semiconductor substrate comprises spacer image transfer methods using a bulk substrate.

5. The method of claim 1 , wherein the forming of the hardmask dielectric on the semiconductor substrate contacting the fin structure sidewalls comprises:

depositing a dielectric material for the hardmask dielectric over the fin structures; and

planarizing the dielectric material for the hardmask dielectric so that the upper surface of the dielectric material is coplanar with the upper surface of the fin structures.

6. The method of claim 1 , wherein said removing portions of the fin structures present on the isolation regions of the substrate to form the fin trenches comprises:

forming an etch mask over the portions of the fin structures present on the active regions, wherein the portions of the fin structures over the isolation regions of the substrate are exposed; and

etching the portions of the fin structures over the isolation regions of the substrate are exposed selectively to the etch mask.

7. The method of claim 1 , wherein said forming the dielectric fin in the fin trenches comprises depositing a dielectric selected from the group consisting of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, silicon carbon boron nitride and combinations thereof.

8. A method for forming a semiconductor device comprising:

forming a plurality of composite fin structures across a semiconductor substrate including active regions and isolation regions, wherein the composite fin structures include semiconductor fin portions over the active regions and dielectric fin portions over the isolation regions, said forming the plurality of composite fin structures comprising forming a plurality of semiconductor fin structures across the semiconductor substrate including the active regions and the isolation regions, forming a hardmask dielectric on the semiconductor substrate contacting the semiconductor fin structure sidewalls, wherein an upper surface of the semiconductor fin structures is exposed, removing portions of the semiconductor fin structures present on the isolation regions of the substrate to form fin trenches having sidewalls defined by the hard mask, wherein portions of the semiconductor fin structures present on the active regions of the substrate remain to provide the semiconductor fin portion, and forming the dielectric fin portions in the fin trenches adjacent to the semiconductor fin portions present on the active regions of the substrate;

forming gate structures on a channel region of the semiconductor fin portions present on the active regions of the substrate and the dielectric fin portions on the isolation regions; and

forming epitaxial source and drain regions on source and drain portions of the semiconductor fin portions present on the active region, wherein the dielectric fin portions support the gate structure over the isolation regions.

9. The method of claim 8 , wherein the semiconductor fin portions are comprised of a semiconductor material selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with carbon (Si:C), type III-V semiconductors and combinations thereof.

10. The method of claim 8 , wherein the dielectric fin portions are comprised of a dielectric selected from the group consisting of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, silicon boron carbon nitride, and combinations thereof.

11. The method of claim 10 , wherein the dielectric fin portions are etch resistant to etchant chemicals of the precursors employed in the forming of the epitaxial source and drain regions on source and drain portions of the fin structures.

12. The method of claim 8 , wherein the epitaxial source and drain regions are merged source and drain regions extending into contact with the source and drain fin portions of adjacent fin structures.

13. The method of claim 12 , wherein the epitaxial source and drain regions are comprised a semiconductor material selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with carbon (Si:C), type III-V semiconductors and combinations thereof.