Overlap capacitance nanowire

1. A method for fabricating a nanowire, comprising:

etching exposed portions of a substrate to provide an unetched raised portion, the substrate having a first set of structures formed thereon and a dummy structure formed over at least a portions of the substrate and the first set of structures;

forming first spacers about a periphery of the dummy structure and the unetched raised portion;

etching the substrate to form controlled undercut etched portions around a portion of the substrate below the dummy structure;

forming second spacers in the controlled undercut etched portions;

removing the dummy structure;

etching the substrate to release the first set of structures; and

forming gate structures including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures such that the second spacers are employed to align edges of the bottom gate to the top gate.

2. The method as recited in claim 1 , wherein forming gate structures includes forming metal gate structures.

3. The method as recited in claim 1 , wherein forming gate structures includes forming the top gate and the bottom gate such that edges of the top gate and bottom gate are aligned.

4. The method as recited in claim 1 , wherein forming gate structures includes forming the bottom gate between the second spacers.

5. The method as recited in claim 1 , wherein etching the substrate to release the first set of structures includes etching the portion of the substrate below the dummy structure to release the first set of structures.

6. The method as recited in claim 1 , wherein etching exposed portions of the substrate includes etching exposed portions of the substrate that are not masked by the dummy structure or the first set of structures.

7. The method as recited in claim 1 , wherein etching the substrate to form controllable undercut etched portions includes etching a portion of the substrate below the first spacers.

8. The method as recited in claim 1 , wherein the first set of structures includes one or more fin structures.

9. The method as recited in claim 1 , wherein the dummy structure includes polysilicon.

10. The method as recited in claim 1 , further comprising forming source/drain regions with interlayer dielectic regions formed thereon.

11. A method for fabricating a nanowire, comprising:

patterning fin structures on a substrate;

forming a dummy structure over portions of the substrate and the fin structures;

etching exposed portions of the substrate to provide an unetched raised portion;

forming first sidewall spacers about a periphery of the dummy structure and the unetched raised portion;

etching the substrate to form controlled undercut etched portions around a portion of the substrate below the dummy structure;

forming second spacers in the controlled undercut etched portions;

forming source/drain regions with interlayer dielectic regions formed thereon;

removing the dummy structure;

etching the substrate to release the fin structures; and

forming metal gate structures including a top gate formed above the fin structures and a bottom gate formed below the fin structures to provide a nanowire such that the second spacers are employed to align edges of the bottom gate to the top gate.

12. The method as recited in claim 11 , wherein forming gate structures includes forming a bottom gate between the second spacers.

13. The method as recited in claim 11 , wherein etching the substrate to release the fin structures includes etching the portion of the substrate below the dummy structure to release the fin structures.

14. The method as recited in claim 11 , wherein etching exposed portions of the substrate includes etching exposed portions of the substrate that are not masked by the dummy structure or the fin structures.

15. The method as recited in claim 11 , wherein the dummy structure includes polysilicon.