Forming gates with varying length using sidewall image transfer

1. A chip, comprising:

a plurality of first transistors in a first region; and

a plurality of second transistors in a second region, wherein a gap between adjacent first transistors has a same width as a gap between adjacent second transistors, and wherein gates of the second transistors have a length substantially the same as twice a length of two adjacent first transistors plus the distance between said two adjacent first transistors.

2. The chip of claim 1 , comprising twice as many first transistors as second transistors.

3. The chip of claim 2 , wherein a number of second transistors is a multiple of two.

4. The chip of claim 1 , wherein the plurality of first transistors are fin field effect transistors.

5. The chip of claim 4 , wherein the plurality of second transistors are fin field effect transistors.

6. The chip of claim 1 , wherein the first transistors are digital logic devices and wherein the second transistors are analog devices.

7. The chip of claim 1 , wherein the first and second transistors each comprise respective gates formed on a planar semiconductor substrate.

8. The chip of claim 7 , wherein the first and second transistors further comprise source and drain regions formed within the planar semiconductor substrate.

9. The chip of claim 7 , wherein the respective gates of the first and second transistors are fin structures.

10. A chip, comprising:

a plurality of first digital logic transistors in a first region comprising respective gates formed on respective channel regions; and

a plurality of second analog transistors in a second region comprising respective gates formed on respective channel regions, wherein a gap between adjacent first transistors has a same width as a gap between adjacent second transistors, and wherein gates of the second transistors have a length substantially the same as twice a length of two adjacent first transistors plus the distance between said two adjacent first transistors.

11. The chip of claim 10 , comprising twice as many first transistors as second transistors.

12. The chip of claim 11 , wherein a number of second transistors is a multiple of two.

13. The chip of claim 10 , wherein the plurality of first transistors are fin field effect transistors.

14. The chip of claim 13 , wherein the plurality of second transistors are fin field effect transistors.

15. The chip of claim 10 , wherein the first and second transistors further comprise source and drain regions formed within the planar semiconductor substrate.

16. The chip of claim 10 , wherein the respective gates of the first and second transistors are fin structures.

17. A chip, comprising:

a plurality of first digital logic transistors in a first region comprising respective gate fin structures formed on respective channel regions; and

an even number of second analog transistors in a second region comprising respective gate fin structures formed on respective channel regions, there being half as many second transistors as first transistors, wherein a gap between adjacent first transistors has a same width as a gap between adjacent second transistors, and wherein gates of the second transistors have a length substantially the same as twice a length of two adjacent first transistors plus the distance between said two adjacent first transistors.

18. The chip of claim 17 , wherein the plurality of first transistors are fin field effect transistors.

19. The chip of claim 18 , wherein the plurality of second transistors are fin field effect transistors.

20. The chip of claim 17 , wherein the first and second transistors further comprise source and drain regions formed within the planar semiconductor substrate.