Fin cut during replacement gate formation
View Patent ↗A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
1. A semiconductor structure, comprising:
a plurality of fins formed over a semiconductor layer formed over a substrate;
an oxide formed in direct contact with the plurality of fins;
a cut created over the oxide to define a first portion of the plurality of fins and a second portion of the plurality of fins that are exposed by the cut including a set of fins to be cut, where the cut is employed to remove the oxide from the second portion of the plurality of fins;
a replacement gate stack, wherein portions of the replacement gate stack are etched to remove the second portion of the plurality of fins to form recesses within the semiconductor layer; and
a spacer formed within the recesses of the semiconductor layer and in direct contact with the first portion of the plurality of fins.
2. The semiconductor structure of claim 1 , wherein the spacer assumes the shape of the first portion of the plurality of fins.
3. The semiconductor structure of claim 2 , wherein the spacer is a non-conducting dielectric layer.
4. The semiconductor structure of claim 1 , wherein the second portion of the plurality of fins are cut during etching of the replacement gate stack.
5. The semiconductor structure of claim 1 , wherein a portion of the oxide is removed before deposition of the replacement gate stack.
6. The semiconductor structure of claim 1 , wherein the replacement gate stack includes a dummy gate.
7. The semiconductor structure of claim 1 , wherein the recesses do not extend into the substrate.
8. The semiconductor structure of claim 1 , wherein each of the plurality of fins is formed by Si.
9. The semiconductor structure of claim 1 , wherein each of the plurality of fins is formed by SiGe.
10. A semiconductor structure, comprising:
a plurality of fins formed over a substrate;
a dielectric layer deposited over the plurality of fins;
a cut created over an oxide formed in direct contact with the plurality of fins to define a first portion of the plurality of fins and a second portion of the plurality of fins that are exposed by the cut including a set of fins to be cut, such that the cut is employed to remove the dielectric layer from the second portion of the plurality of fins to be cut; and
a spacer formed within recesses of the dielectric layer and in direct contact with the first portion of the plurality of fins.
11. The semiconductor structure of claim 10 , wherein the plurality of fins are SiGe fins.
12. The semiconductor structure of claim 10 , wherein the plurality of fins are Si fins.
13. The semiconductor structure of claim 10 , wherein the spacer is a non-conducting dielectric layer.
14. The semiconductor structure of claim 10 , wherein the second portion of the plurality of fins are cut.
15. The semiconductor structure of claim 10 , wherein the recesses do not extend into the substrate.
16. The semiconductor structure of claim 15 , wherein the spacer assumes the shape of the first portion of the plurality of fins.
17. The semiconductor structure of claim 10 , wherein the second portion of the plurality of fins are cut by patterning an area of the second portion of the plurality of fins.