Wafer-scale package structures with integrated antennas
View Patent ↗Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip.
1. A chip package, comprising:
an RFIC (radio frequency integrated circuit) chip comprising a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate;
an antenna structure comprising an antenna substrate and a planar antenna radiator fowled on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material;
an interface layer connecting the antenna structure to the BEOL structure of the RFIC chip; and
an antenna feed line formed as part of the BEOL structure of the RFIC chip.
2. The chip package of claim 1 , further comprising contact pads formed on the surface of the antenna substrate and conductive vias foamed through the antenna substrate, wherein the conductive vias form electrical interconnects between the BEOL structure of the RFIC chip and the contact pads formed on the surface of the antenna substrate.
3. The chip package of claim 1 , further comprising an antenna ground plane formed as part of the BEOL structure of the RFIC chip.
4. The chip package of claim 1 , wherein the antenna substrate is a low loss silicon substrate.
5. The chip package of claim 1 , wherein the antenna substrate comprises a stack of two or more antenna substrate layers.
6. The chip package of claim 1 , wherein a footprint of the RFIC chip is larger than a footprint of the antenna structure.
7. The chip package of claim 1 , wherein a footprint of the RFIC chip is smaller than a footprint of the antenna structure.
8. The chip package of claim 1 , wherein the interface layer between the antenna structure and the BEOL structure comprises a plurality of metal stubs or rings and under fill material, which bond the antenna structure to the BEOL structure.
9. The chip package of claim 1 , wherein the low loss semiconductor material is high resistivity silicon, silica, or quartz.
10. The chip package of claim 5 , wherein at least one antenna substrate layer is a low loss silicon substrate and at least another antenna substrate layer is a silica substrate.
11. The chip package of claim 5 , further comprising a metallization pattern disposed between two adjacent antenna substrate layers.
12. The chip package of claim 11 , wherein the metallization pattern is an antenna ground plane that is disposed between the antenna radiator formed on the surface of the antenna substrate and an antenna feed line formed in the BEOL structure.
13. The chip package of claim 11 , wherein the metallization pattern is a second antenna radiator.
14. The chip package of claim 11 , wherein the metallization pattern is at least a portion of an electrical interconnect.
15. An apparatus, comprising;
a chip package, comprising:
an RFIC (radio frequency integrated circuit) chip comprising a semiconductor substrate having an active surface and an inactive surface; and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate;
an antenna structure comprising an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material; and
an interface layer connecting the antenna structure to the BEOL structure of the RFIC chip;
a circuit board, wherein the chip package is mounted to the circuit board; and
electrical interconnect structures providing DC supply, ground, control and I/O baseband signal lines between the RFIC chip and the circuit board.
16. The apparatus of claim 15 , wherein the electrical interconnect structures comprise:
contact pads formed on the surface of the antenna substrate;
contact pads formed on the surface of the circuit board;
wire bonds formed between contacts pads on the surface of the antenna substrate and the circuit board; and
conductive vias and metal traces formed in the antenna substrate connecting the contact pads on the surface of the antenna substrate with contacts in the BEOL structure.
17. The apparatus of claim 15 , wherein the electrical interconnect structures comprise:
conductive vias that are formed through the semiconductor substrate of the RFIC chip from the active surface to the inactive surface; and
contact pads on a the inactive surface of the semiconductor subset of the RFIC chip forming electrical bonds to contact pads on the circuit board.
18. The apparatus of claim 15 , wherein the antenna structure is bonded to the circuit board, wherein the circuit board has an opening forming a window for electromagnetic radiation to be emitted or captured by the antenna radiator.
19. The apparatus of claim 15 , wherein the antenna structure is bonded to the circuit board, wherein the circuit board has an opening forming a window through which the RFIC chip is inserted.
20. The apparatus of claim 15 , wherein the inactive surface of the semiconductor substrate of the RFIC chip is bonded to the circuit board.
21. The apparatus of claim 15 , wherein the low loss semiconductor material is high resistivity silicon, silica, or quartz.