Punch through stopper in bulk finFET device
View Patent ↗A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
1. A finFET semiconductor device comprising:
a fin structure including a channel region portion, a source region portion, a drain region portion, and a punch through stopper dopant region present at a base of the fin structure for the source region portion and the drain region portion, wherein at least one of the source region portion and the drain region portion has a stepped sidewall with a base width that is greater than a width of an upper surface of said at least one of the source region portion and the drain region portion, wherein the base width ranges from 10 nm to 15 nm;
and
source and drain regions on the source region portion and the drain region portion of the fin structure, wherein an entirety of the stepped sidewall of the fin structure is encapsulated between a dielectric fill material and said source and drain regions.
2. The finFET semiconductor device of claim 1 , wherein the fin structure is present on an etched portion of a bulk semiconductor substrate.
3. The finFET semiconductor device of claim 1 , wherein the punch through stopper dopant region is doped to a conductivity type that is opposite a conductivity type of the source region portion and drain region portion of the fin structure.
4. The FinFET semiconductor device of claim 1 , wherein the gate structure includes at least one gate dielectric and at least one metal gate conductor.
5. The FinFET semiconductor device of claim 1 , wherein the fin structure is present on a bulk semiconductor substrate.
6. A semiconductor device comprising:
a vertically orientated structure including a channel region portion, a source region portion, a drain region portion, and a punch through stopper dopant region present at a base of a fin structure for the source region portion and the drain region portion, wherein at least one of the source region portion and the drain region portion has a stepped sidewall with a base width that is greater than a width of an upper surface of said at least one of the source region portion and the drain region portion, wherein the base width ranges from 10 nm to 15 nm; and
epitaxial source and drain regions on the source portion and the drain region portion on the stepped sidewall to encapsulate the stepped sidewall between said epitaxial source and drain regions and a dielectric fill material.
7. The semiconductor device of claim 6 , wherein the fin structure is present on an etched portion of a bulk semiconductor substrate.
8. The semiconductor device of claim 6 , wherein the punch through stopper dopant region is doped to a conductivity type that is opposite a conductivity type of the source region portion and drain region portion of the vertically orientated structure.
9. The semiconductor device of claim 6 further comprising a gate structure on the channel portion of the vertically orientated structure including at least one gate dielectric and at least one gate conductor.
10. A semiconductor device comprising:
a fin structure including a channel region portion, a source region portion, a drain region portion, and a punch through stopper dopant region present at a base of the fin structure for the source region portion and the drain region portion, wherein at least one of the source region portion and the drain region portion has a stepped sidewall; wherein a base width of the fin structure ranges from 10 nm to 15 nm, and an upper surface of the fin structure has a width that ranges from 8 nm to 10 nm;
a gate structure present on the channel region portion of the fin structure; and
epitaxial source and drain regions on the source region portion and the drain region portion of the fin structure, wherein an entirety of the stepped sidewall of the fin structure is encapsulated between said epitaxial source and drain regions and a dielectric fill material.
11. The semiconductor device of claim 10 , wherein the fin structure is present on an etched portion of a bulk semiconductor substrate.
12. The semiconductor device of claim 10 , wherein the punch through stopper dopant region is doped to a conductivity type that is opposite a conductivity type of the source region portion and drain region portion of the fin structure.
13. The semiconductor device of claim 10 , wherein the gate structure includes at least one gate dielectric and at least one metal gate conductor.
14. The semiconductor device of claim 10 , wherein the fin structure includes a semiconductor selected from the group consisting of silicon, strained silicon, a silicon carbon alloy, silicon germanium, a silicon germanium and carbon alloy, silicon alloys, germanium, germanium alloys, gallium arsenic, indium arsenic, indium phosphide, III/V and II/VI compound semiconductors and combinations thereof.
15. The semiconductor device of claim 10 , wherein the semiconductor device is a FinFET.