Nanosheet MOSFET with full-height air-gap spacer
A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.
1. A method of making features of a semiconductor device, the method comprising:
forming a nanosheet stack comprising a first nanosheet in contact with a substrate and a second nanosheet disposed on the first nanosheet;
depositing a dielectric layer on the nanosheet stack;
forming a gate comprising a sacrificial gate material on the nanosheet stack and the dielectric layer, a gate spacer positioned along a sidewall of the gate;
removing an end portion of the first nanosheet to form a lateral recess beneath the gate spacer;
depositing a dielectric material in the lateral recess;
forming a source/drain on the substrate adjacent to the gate;
replacing the sacrificial gate material with a conductive gate stack;
removing remaining portions of the first nanosheet; and
removing the gate spacer to expose the dielectric layer on the nanosheet stack and form an air gap spacer.
2. The method of claim 1 , further comprising removing a portion of the conductive gate stack to form a recess and depositing a dielectric material in the recess to form a gate cap.
3. The method of claim 1 , wherein the air gap spacer is positioned in contact with the dielectric layer.
4. The method of claim 3 , further comprising forming a source/drain contact on the source/drain and adjacent to the gate spacer, and wherein the air gap spacer is positioned in contact with the source/drain contact.
5. The method of claim 1 , wherein a gate cap is positioned on the gate stack, and the air gap spacer contacts the gate cap.
6. The method of claim 1 , wherein the air gap spacer has a height in a range from about 10 to about 150 nanometers (nm).
7. The method of claim 1 , wherein the first nanosheet is silicon, silicon carbide, germanium, silicon germanium, silicon germanium carbon, gallium arsenide, indium arsenide, indium phosphide, or any combination thereof.
8. The method of claim 1 , wherein the second nanosheet is silicon, silicon carbide, germanium, silicon germanium, silicon germanium carbon, gallium arsenide, indium arsenide, indium phosphide, or any combination thereof.
9. The method of claim 1 , wherein the dielectric material in the lateral recess and the dielectric layer on an exposed surface of the second nanosheet are a low-k dielectric material.
10. A method of making a semiconductor device, the method comprising:
forming a nanosheet stack comprising a first nanosheet in contact with a substrate and a second nanosheet disposed on the first nanosheet;
depositing a dielectric layer on the nanosheet stack;
forming a gate comprising a sacrificial gate material on the nanosheet stack and the dielectric layer, a gate spacer positioned along a sidewall of the gate;
removing an end portion of the first nanosheet to form a lateral recess beneath the gate spacer;
depositing a dielectric material in the lateral recess;
forming a source/drain on the substrate adjacent to the gate;
replacing the sacrificial gate material with a conductive gate stack;
removing remaining portions of the first nanosheet; and
forming a source/drain contact on the source/drain and adjacent to the gate spacer; and
removing the gate spacer to expose the dielectric layer on the nanosheet stack and form an air gap spacer.
11. The method of claim 10 , further comprising removing a portion of the conductive gate stack to form a recess and depositing a dielectric material in the recess to form a gate cap.
12. The method of claim 10 , wherein the air gap spacer is positioned in contact with the dielectric layer.
13. The method of claim 12 , wherein the air gap spacer is positioned in contact with the source/drain contact.
14. The method of claim 10 , wherein a gate cap is positioned on the gate stack, and the air gap spacer contacts the gate cap.
15. The method of claim 10 , wherein the air gap spacer has a height in a range from about 10 to about 150 nanometers (nm).
16. The method of claim 10 , wherein the first nanosheet is silicon, silicon carbide, germanium, silicon germanium, silicon germanium carbon, gallium arsenide, indium arsenide, indium phosphide, or any combination thereof.
17. The method of claim 10 , wherein the second nanosheet is silicon, silicon carbide, germanium, silicon germanium, silicon germanium carbon, gallium arsenide, indium arsenide, indium phosphide, or any combination thereof.
18. The method of claim 10 , wherein the dielectric material in the lateral recess and the dielectric layer on an exposed surface of the second nanosheet are a low-k dielectric material.