Stacked nanowire devices
View Patent ↗A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
1. A semiconductor device comprising:
first stack of nanowires arranged on a substrate comprising a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate,
a second stack of nanowires comprising a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and
the first nanowire and the second nanowire comprising a first semiconductor material and the third nanowire and the fourth nanowire comprising a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
2. The device of claim 1 , wherein the first nanowire and the second nanowire are substantially co-planar in a second plane, the second plane substantially perpendicular to the first plane.
3. The device of claim 1 , wherein the first semiconductor material includes silicon.
4. The device of claim 1 , wherein the second semiconductor material includes silicon germanium.
5. The device of claim 1 , further comprising a first gate stack arranged over a channel region of the first stack of nanowires.
6. The device of claim 5 , further comprising spacers arranged adjacent to the first gate stack.
7. The device of claim 6 , further comprising a source/drain region arranged adjacent to the spacers.
8. The device of claim 7 wherein the first nanowire extends through the spacer and into the source/drain region.
9. The device of claim 1 , further comprising a second gate stack arranged over a channel region of the second stack of nanowires.
10. The device of claim 9 , further comprising spacers arranged adjacent to the second gate stack.
11. The device of claim 10 , further comprising a source/drain region arranged adjacent to the spacers.
12. A semiconductor device comprising:
first stack of nanowires arranged on a substrate comprising a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate,
a second stack of nanowires comprising a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire,
the first nanowire and the second nanowire comprising a first semiconductor material and the third nanowire and the fourth nanowire comprising a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material, and
a first gate stack arranged over a channel region of the first nanowire and a channel region of the second nanowire.
13. The device of claim 12 , wherein the first nanowire and the second nanowire are substantially co-planar in a second plane, the second plane substantially perpendicular to the first plane.
14. The device of claim 12 , wherein the first semiconductor material includes silicon.
15. The device of claim 12 , wherein the second semiconductor material includes silicon germanium.
16. The device of claim 12 , further comprising spacers arranged adjacent to the first gate stack.
17. The device of claim 16 , further comprising a source/drain region arranged adjacent to the spacers.
18. The device of claim 17 , wherein the first nanowire extends through the spacer and into the source/drain region.
19. The device of claim 12 , further comprising a second gate stack arranged over a channel region of the second stack of nanowires.
20. The device of claim 19 , further comprising spacers arranged adjacent to the second gate stack.