IP Library Granted Patent US 9,935,051
Granted Patent B2
US 9,935,051 · App. 15/240,700 · Granted Apr 3, 2018

Multi-level metallization interconnect structure

Inventors: Praneet Adusumilli (Albany, NY); Alexander Reznicek (Troy, NY); Oscar van der Straten (Guilderland Center, NY)
Assignee: International Business Machines Corporation
H01L23/5283H01L21/76804H01L21/76843H01L21/76877H01L23/53266H01L27/0886
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Quick Facts
Patent No.
US 9,935,051
App. No.
15/240,700
Granted
Apr 3, 2018
Kind
B2
Abstract

A semiconductor structure is provided that includes a contact structure containing a gouged upper surface embedded in at least a middle-of-the-line (MOL) dielectric material, wherein the contact structure contacts an underlying doped semiconductor material structure. A first metallization structure containing a gouged upper surface is in contact with the gouged upper surface of the contact structure and embedded in a first interconnect dielectric material. A second metallization structure is in contact with the gouged upper surface of the first metallization structure and embedded at least within a second interconnect dielectric material.

Claims (21)

1. A semiconductor structure comprising:

a contact structure containing a gouged feature having a concave curvature and embedded in at least a middle-of-the-line (MOL) dielectric material, wherein said contact structure contacts an underlying doped semiconductor material structure;

a first metallization structure in contact with said gouged feature of said contact structure and embedded in a first interconnect dielectric material, said first metallization structure contains a gouged feature having a concave curvature; and

a second metallization structure in contact with said gouged feature of said first metallization structure and embedded at least within a second interconnect dielectric material.

2. The semiconductor structure of claim 1 , wherein each of said contact structure, said first metallization structure, and said second metallization structure comprises a low resistivity metal or metal alloy.

3. The semiconductor structure of claim 2 , wherein said low resistivity metal or metal alloy is selected from the group consisting of cobalt (Co), ruthenium (Ru), molybdenum (Mo), osmium (Os), iridium (Ir) and rhodium (Rh).

4. The semiconductor structure of claim 1 , wherein said first metallization structure has a rounded bottommost surface and said second metallization structure has a rounded bottommost surface that extends beneath a topmost surface of said first metallization structure.

5. The semiconductor structure of claim 1 , further comprising a diffusion barrier liner located on sidewalls and a bottommost surface of each of said contact structure, said first metallization structure, and said second metallization structure.

6. The semiconductor structure of claim 1 , further comprising a dielectric capping layer separating said MOL dielectric material from said first interconnect dielectric material, wherein said contact structure has a topmost surface that is coplanar with said dielectric capping layer.

7. The semiconductor structure of claim 6 , further comprising another dielectric capping layer separating said first interconnect dielectric material from said second interconnect dielectric material, wherein said first metallization structure has a topmost surface that is located entirely beneath said another dielectric capping layer and a bottom portion of said second metallization structure is embedded in said another dielectric capping layer.

8. The semiconductor structure of claim 1 , wherein said doped semiconductor material structure comprises a plurality of diamond shaped doped semiconductor material subunits that are merged.

9. The semiconductor structure of claim 1 , wherein a metal semiconductor alloy layer is present on a surface of said doped semiconductor material structure.

10. The semiconductor structure of claim 1 , wherein said doped semiconductor material structure is present on a portion of at least one semiconductor fin.

11. A semiconductor structure comprising:

a contact structure containing a gouged feature and embedded in at least a middle-of-the-line (MOL) dielectric material, wherein said contact structure contacts an underlying doped semiconductor material structure and has a topmost surface that is coplanar with said MOL dielectric material;

a first metallization structure in contact with said gouged feature of said contact structure and embedded in a first interconnect dielectric material, said first metallization structure contains a gouged feature; and

a second metallization structure in contact with said gouged feature of said first metallization structure and embedded at least within a second interconnect dielectric material.

12. A semiconductor structure comprising:

a contact structure containing a gouged feature and embedded in at least a middle-of-the-line (MOL) dielectric material, wherein said contact structure contacts an underlying doped semiconductor material structure and comprises a first diffusion barrier liner and a first low resistivity contact metal or metal alloy, wherein a topmost surface of said first low resistivity contact metal or metal alloy is coplanar with topmost surfaces of said first diffusion barrier liner;

a first metallization structure in contact with said gouged feature of said contact structure and embedded in a first interconnect dielectric material, said first metallization structure contains a gouged upper surface and comprises a second diffusion barrier liner and a second low resistivity contact metal or metal alloy, wherein a topmost surface of said second low resistivity contact metal or metal alloy is coplanar with topmost surfaces of said second diffusion barrier liner; and

a second metallization structure in contact with said gouged feature of said first metallization structure and embedded at least within a second interconnect dielectric material, wherein said second metallization structure comprises a third diffusion barrier liner and a third low resistivity contact metal or metal alloy, wherein a topmost surface of said third low resistivity contact metal or metal alloy is coplanar with topmost surfaces of said third diffusion barrier liner.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0771 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0868 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2016
From: ADUSUMILLI, PRANEET; REZNICEK, ALEXANDER; VAN DER STRATEN, OSCAR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039478/0251 →
Continuity (1)
Related Publication 20180053721A1 · Feb 22, 2018