Punch through stopper in bulk finFET device
View Patent ↗A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
1. A method for forming a semiconductor device comprising:
forming a gate structure on a channel region portion of a fin structure after forming an isolation region;
forming a spacer on the gate structure;
exposing a lower portion of a sidewall of the fin structure;
forming a doped material on the lower portion of the fin structure, wherein said forming the doped material on the exposed lower portion of the sidewall of the fin structure comprises epitaxial deposition of a semiconductor material that is in situ doped with an n-type or p-type dopant; and
diffusing dopant from the doped material to a base portion of the fin structure.
2. The method of claim 1 , wherein the fin structure is formed from a bulk semiconductor substrate.
3. The method of claim 1 , further comprising forming the isolation region adjacent to the fin structure.
4. The method of claim 3 , wherein exposing said lower portion of the sidewall of the fin structure comprises recessing the isolation region.
5. The method of claim 1 , wherein the dopant that is diffused from the doped material to the base portion of the fin structure has an opposite conductivity as a source region dopant and a drain region dopant.
6. The method of claim 1 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after said diffusing the dopant from the doped material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure.
7. The method of claim 6 , wherein the forming of the replacement gate on the fin structure comprises:
depositing at least one sacrificial material layer on the fin structure; and
patterning the at least one sacrificial material layer to remove the sacrificial material from a source region portion and a drain region portion of the fin structure so that a remaining portion of the at least one sacrificial material layer is present on the channel region portion of the fin structure.
8. The method of claim 1 , wherein the forming of the spacer comprises:
conformally depositing a blanket layer of a dielectric material; and
anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure.
9. The method of claim 1 , wherein said epitaxial semiconductor material is silicon.
10. The method of claim 1 , wherein said diffusing dopant from the doped material to a base portion of the fin structure comprises thermal annealing selected from the group consisting of rapid thermal anneal, laser annealing and combinations thereof.
11. A method for forming a semiconductor device comprising:
forming a gate structure on a channel region portion of a fin structure after forming an isolation region;
forming a sacrificial spacer on the gate structure;
exposing a lower portion of a sidewall of the fin structure;
forming a doped material on the lower portion of the fin structure, wherein said forming the doped material on the exposed lower portion of the sidewall of the fin structure comprises epitaxial deposition of a semiconductor material that is in situ doped with an n-type or p-type dopant;
diffusing dopant from the doped material to a base portion of the fin structure;
removing the sacrificial spacer; and
forming source and drain regions in contact with an upper portion of the sidewall of the fin structure.
12. The method of claim 11 , wherein the fin structure is formed from a bulk semiconductor substrate.
13. The method of claim 11 , further comprising forming the isolation region adjacent to the fin structure.
14. The method of claim 13 , wherein exposing said lower portion of the sidewall of the fin structure comprises recessing the isolation region.
15. The method of claim 11 , wherein the dopant that is diffused from the doped material to the base portion of the fin structure has an opposite conductivity as a source region dopant and a drain region dopant.
16. The method of claim 11 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after said diffusing the dopant from the doped material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure.
17. The method of claim 16 , wherein the forming of the replacement gate on the fin structure comprises:
depositing at least one sacrificial material layer on the fin structure; and
patterning the at least one sacrificial material layer to remove the sacrificial material from a source region portion and a drain region portion of the fin structure so that a remaining portion of the at least one sacrificial material layer is present on the channel region portion of the fin structure.
18. The method of claim 11 , wherein the forming of the sacrificial spacer comprises:
conformally depositing a blanket layer of a dielectric material; and
anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure.
19. The method of claim 11 , wherein said epitaxial semiconductor material is silicon.
20. The method of claim 11 , wherein said diffusing dopant from the doped material to a base portion of the fin structure comprises thermal annealing selected from the group consisting of rapid thermal anneal, laser annealing and combinations thereof.