Asymmetric finFET memory access transistor

1. A method for fabricating a field effect transistor device, the method comprising:

forming a doped layer on a semiconductor substrate;

forming a sacrificial layer on the doped layer;

forming a fin on the sacrificial layer, the fin having a nitride portion and a semiconductor portion;

etching to remove a portion of the semiconductor portion of the fin to expose a portion of the doped layer;

growing a semiconductor material from the exposed portion of the doped layer;

depositing a first nitride layer on the fin;

patterning and etching to remove portions of the nitride layer and define a channel region on the fin;

etching to remove the sacrificial layer and form a void that exposes a portion of the doped layer;

depositing an insulator material in the void and the channel region of the fin;

etching to remove a portion of the insulator material and expose the channel region of the fin; and

forming a gate stack over the channel region of the fin.

2. The method of claim 1 , wherein the sacrificial layer includes a silicon germanium material.

3. The method of claim 1 , further comprising forming a spacer on the fin and around the grown semiconductor material prior to depositing the nitride layer on the fin.

4. The method of claim 3 , further comprising removing the spacer and depositing a second nitride layer on the first nitride layer.

5. The method of claim 1 , wherein the fin includes a silicon material.

6. The method of claim 1 , wherein the insulator material includes an oxide material.

7. The method of claim 1 , wherein the fin is formed by an epitaxial growth and lithographic patterning and etching process.

8. The method of claim 1 , semiconductor material grown from the exposed portion of the doped layer is a doped epitaxially grown silicon material.

9. The method of claim 1 , further comprising implanting dopants adjacent to the channel region of the fin prior to forming the gate stack and annealing to form a source region having a graduated concentration of dopants.

10. A method for fabricating a field effect transistor device, the method comprising:

forming a doped layer on a semiconductor substrate;

forming a sacrificial layer on the doped layer;

growing a semiconductor layer on the sacrificial layer;

patterning the semiconductor layer to form a fin;

removing a portion of the fin;

forming a nitride portion of the fin;

patterning a hardmask layer on the fin;

etching to remove an exposed portion of the fin and the sacrificial layer to form a cavity that exposes a portion of the doped layer;

growing a semiconductor material in the cavity;

forming a spacer on the fin and around the grown semiconductor material;

depositing a first nitride layer on the fin;

removing the spacer;

depositing a second nitride layer on the fin;

patterning and etching to remove portions of the first nitride layer and the second nitride layer, and define a channel region on the fin;

etching to remove the sacrificial layer and form a void that exposes a portion of the doped layer;

depositing an insulator material in the void and the channel region of the fin;

etching to remove a portion of the insulator material and expose the channel region of the fin; and

forming a gate stack over the channel region of the fin.

11. The method of claim 10 , wherein the sacrificial layer includes a silicon germanium material.

12. The method of claim 10 , wherein the fin includes a silicon material.

13. The method of claim 10 , wherein the insulator material includes an oxide material.

14. The method of claim 10 , wherein the semiconductor material grown in the cavity includes an epitaxially grown material.

15. The method of claim 10 , wherein the etching to remove the sacrificial layer includes an isotropic etching process.