IP Library Granted Patent US 10,355,094
Granted Patent B2
US 10,355,094 · App. 15/591,396 · Granted Jul 16, 2019

Low resistance contact structures for trench structures

Inventors: Praneet Adusumilli (Albany, NY); Alexander Reznicek (Troy, NY); Oscar van der Straten (Guilderland Center, NY); Chih-Chao Yang (Glenmont, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/41791H01L21/76841H01L21/76843H01L21/76846H01L21/76877H01L21/76897H01L23/485H01L23/5283H01L23/535H01L23/53238H01L23/53252H01L23/53266H01L27/0886H01L27/1211H01L29/0649H01L29/401H01L29/41783H01L29/456H01L29/66795H01L29/785H01L21/28518H01L21/76855
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Quick Facts
Patent No.
US 10,355,094
App. No.
15/591,396
Granted
Jul 16, 2019
Kind
B2
Abstract

An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 Å to 100 Å.

Claims (17)

1. A semiconductor device comprising:

a fin structure providing a channel region of the semiconductor device, wherein source and drain regions that are positioned on opposing sides of the channel region are present on source and drain portions of the fin structure;

openings through a dielectric layer, the opening to the source and drain portions of the fin structure;

a titanium silicide region that is in direct contact with the at least one contact surface of the source and drain regions, the titanium silicide region extending from a silicide forming layer that is present sidewalls of the opening through the dielectric layer to the source and drain portions of the fin structure;

a gate structure on the channel region of the semiconductor device; and

a contact to at least one of the titanium silicide region of the source and drain regions, the contact including a conformal titanium liner that is present on the sidewalls of a trench through an interlevel dielectric to the source and drain regions, and a metal fill comprising copper fill promoting liner of ruthenium, wherein a metal nitride liner is present between the ruthenium liner and the conformal titanium liner, the contact having a resistance of 45 micro ohms per cm or less.

2. The semiconductor device of claim 1 , wherein the conformal titanium liner comprises 100 wt. % titanium.

3. The semiconductor device of claim 1 , wherein the conformal titanium liner comprises a thickness ranging from 10 Å to 100 Å.

4. The semiconductor device of claim 1 , wherein the copper fill promoting liner is a ruthenium liner.

5. The semiconductor device of claim 1 , wherein the metal nitride liner is selected from the group consisting of tantalum nitride, tungsten nitride and a combination thereof.

6. The semiconductor device of claim 1 , wherein the metal semiconductor alloy is a silicide.

7. The semiconductor device of claim 1 , wherein the silicide is titanium silicide.

8. A semiconductor device comprising:

a fin structure having a metal semiconductor alloy region comprised of a titanium silicide region, the titanium silicide region extending from a silicide forming layer that is present on sidewalls of openings through a dielectric layer to source and drain portions of the fin structure that the metal semiconductor alloy region is present on; and

a contact to at least one of the metal semiconductor alloy region, the contact including a conformal titanium liner that is present on the sidewalls of a trench through an interlevel dielectric to the metal semiconductor alloy region, a metal nitride liner presented on the confirmal titanium liner, a copper promoting liner of ruthenium present on the metal nitride liner, and a metal fill of copper present on the copper promoting liner, the contact having a resistance of 45 micro ohms per cm or less.

9. The semiconductor device of claim 8 , wherein the conformal titanium liner comprises 100 wt. % titanium.

10. The semiconductor device of claim 8 , wherein the conformal titanium liner comprises a thickness ranging from 10 Å to 100 Å.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0462 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0849 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2017
From: ADUSUMILLI, PRANEET; REZNICEK, ALEXANDER; VAN DER STRATEN, OSCAR; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 042322/0539 →
Continuity (3)
Division 15226157 · Aug 2, 2016
Division 14919201 · Oct 21, 2015
Related Publication 20170243825A1 · Aug 24, 2017