Lowering parasitic capacitance of replacement metal gate processes
View Patent ↗The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance.
1. A semiconductor structure comprising:
a gate stack including a gate component structure and a gate electrode disposed on said gate component structure, wherein said gate component structure includes a U-shaped high-k gate dielectric and a U-shaped metal cap disposed on said U-shaped high-k gate dielectric; and
a planarization dielectric material layer contacting sidewalls of said gate electrode and said vertical portions of said U-shaped high-k gate dielectric.
2. The semiconductor structure of claim 1 , wherein said U-shaped high-k gate dielectric has a dielectric constant greater than 3.9.
3. The semiconductor structure of claim 2 , wherein said U-shaped high-k gate dielectric comprises hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.
4. The semiconductor structure of claim 1 , wherein said U-shaped metal cap comprises TiN, TiSiN, TaN, TaSiN, TiTaN, TaRuN, WN, WSiN, or combinations thereof.
5. The semiconductor structure of claim 1 , wherein said planarization dielectric material layer comprises a doped silicate glass, an undoped silicate glass (silicon oxide), an organosilicate glass (OSG), or a porous dielectric material.
6. The semiconductor structure of claim 1 , wherein top surfaces of said vertical portions of said U-shaped high-k gate dielectric and top surfaces of vertical portions of said U-shaped metal cap are located below a top surface of said planarization dielectric material layer.
7. The semiconductor structure of claim 6 , wherein said top surfaces of said vertical portions of said U-shaped high-k gate dielectric are coplanar with said top surfaces of said vertical portions of said U-shaped metal cap.
8. The semiconductor structure of claim 6 , wherein said gate electrode contacts said top surfaces of said vertical portions of said U-shaped high-k gate dielectric and said top surfaces of said vertical portions of said U-shaped metal cap.
9. The semiconductor structure of claim 1 , wherein a lower portion of inner sidewalls of said planarization dielectric material layer laterally contacts said vertical portions of said U-shaped high-k gate dielectric and an upper portion of said inner sidewalls of said planarization dielectric material layer laterally contacts said gate electrode.
10. The semiconductor structure of claim 1 , wherein said gate electrode comprises a work function metal portion and a conductive metal portion disposed on said work function metal portion.
11. The semiconductor structure of claim 10 , wherein said work function metal portion vertically contacts top surfaces of said vertical portions of said U-shaped high-k gate dielectric and top surfaces of vertical portions of said U-shaped metal cap.
12. The semiconductor structure of claim 11 , wherein a lower portion of inner sidewalls of said planarization dielectric material layer laterally contacts said vertical portions of said U-shaped high-k gate dielectric and an upper portion of said inner sidewalls of said planarization dielectric material layer laterally contacts said work function metal portion.
13. The semiconductor structure of claim 11 , wherein sidewalls of said conductive metal portion are vertically coincident with inner sidewalls of said U-shaped metal cap.
14. The semiconductor structure of claim 11 , wherein said work function metal portion comprises a metal-containing material the same as that of said U-shaped metal cap.
15. The semiconductor structure of claim 11 , wherein said work function metal portion comprises TiN, TaC, TaNC, or Ru.
16. The semiconductor structure of claim 11 , wherein said conductive metal portion comprises Al, W, Cu, Pt, Ag, Au, Ru, Ir, Rh, or Re.
17. The semiconductor structure of claim 1 , wherein said gate stack is located over a semiconductor structure.
18. The semiconductor structure of claim 17 , further comprising a source region located within said semiconductor structure and adjoined to a first side of said gate stack, and a drain region located within said semiconductor structure and adjoined to a second side of said gate stack opposite the first side, wherein said planarization dielectric material layer vertically contacts said source region and said drain region.
19. The semiconductor structure of claim 18 , further comprising a source-side contact via structure extending through said planarization dielectric material and contacting said source region, and a drain-side contact via structure extending through said planarization dielectric material and contacting said drain region.