Semiconductor device replacement metal gate with gate cut last in RMG
A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.
1. A method for making a semiconductor structure, the method comprising:
providing a starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region;
patterning a first trench in a mask over the mid-region of the gate and a second trench in the mask over the end-region of the gate;
etching, using the mask, a first trench in the mid-region of the gate and a second trench in the end-region of the gate, the first trench and the second trench being separate trenches formed in different regions of the gate, the first trench comprising a bottom wall formed of the substrate and a plurality of sidewalls formed of a gate metal and a work function metal stack, and the second trench comprising a bottom wall formed of the substrate, a first sidewall formed of a gate spacer, and a second sidewall formed of the gate metal and the work function metal stack; and
depositing a conformal low-k dielectric layer over the structure to fill the first trench and the second trench, and pinch off the first trench formed in the mid-region and the second trench formed in the end-region.
2. The method of claim 1 , wherein the gate is a replacement metal gate.
3. The method of claim 1 , wherein the mask is a photoresist.
4. The method of claim 1 , wherein etching the first trench and the second trench in the gate comprises etching with an anisotropic plasma etch.
5. The method of claim 1 , further comprising depositing an inter-layer dioxide on the conformal low-k dielectric layer.
6. The method of claim 1 , wherein the conformal low-k dielectric layer comprises silicon nitride.
7. The method of claim 1 , wherein etching the first trench and the second trench comprises removing metal residue.
8. The method of claim 1 , wherein the conformal low-k dielectric layer has a thickness of about 3 to about 100 nanometers.
9. The method of claim 1 , further comprising planarizing the structure selectively to the gate metal.
10. The method of claim 9 , wherein planarizing the structure selectively to the gate metal comprises planarizing with chemical mechanical planarization selective to the conformal low-k dielectric layer.
11. The method of claim 10 , wherein planarizing the structure selectively to the gate metal further comprises removing any remaining conformal low-k dielectric layer disposed on top of the gate metal.