Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers
View Patent ↗Methods for fabricating low-resistivity metallic interconnect structures with self-forming diffusion barrier layers are provided, as well as semiconductor devices comprising low-resistivity metallic interconnect structures with self-formed diffusion barrier layers. For example, a semiconductor device includes a dielectric layer disposed on a substrate, an opening etched in the dielectric layer, a metallic liner layer covering sidewall and bottom surfaces of the opening in the dielectric layer, copper material filling the opening to form an interconnect structure, and a self-formed diffusion barrier layer formed in the sidewall surfaces of the opening of the dielectric layer. The self-formed diffusion barrier layer includes manganese atoms which are diffused into the sidewall surfaces of the dielectric layer.
1. A method, comprising:
forming a dielectric layer on a substrate;
patterning the dielectric layer to form an opening in the dielectric layer;
forming a first diffusion barrier layer to cover an upper surface of the dielectric layer and sidewall and bottom surfaces of the opening in the dielectric layer;
etching the first diffusion barrier layer to remove portions of the first diffusion harrier layer on the sidewall surfaces of the opening, while leaving portions of the first diffusion barrier layer on the upper surface of the dielectric layer and on the bottom surface of the opening;
conformally depositing a metallic liner layer to cover exposed surfaces within the opening;
conformally depositing a seed layer over the metallic liner layer, wherein the seed layer comprises a copper-manganese alloy;
depositing a layer of copper material to fill the opening with copper material; and
performing a thermal anneal treatment to cause manganese atoms of the seed layer to diffuse into the sidewall surfaces of the opening in the dielectric layer to form an embedded barrier diffusion layer which is embedded within the sidewall surfaces.
2. The method of claim 1 , wherein the first diffusion barrier layer comprises one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).
3. The method of claim 1 , wherein the embedded barrier diffusion layer comprises one of silicon manganese, manganese carbonate, and manganese oxide.
4. The method of claim 1 , wherein the metallic liner layer comprises cobalt.
5. The method of claim 1 , wherein forming the first diffusion barrier layer comprises depositing the first diffusion barrier layer using a deposition process which is configured to form the diffusion barrier layer with a greater thickness on the upper surface of dielectric layer and on the bottom surface of the opening, as compared to a thickness of the diffusion barrier layer on the sidewalls of the opening.
6. The method of claim 5 , wherein etching the first diffusion barrier layer to remove portions of the first diffusion barrier layer on the sidewall surfaces of the opening, while leaving portions of the first diffusion barrier layer on the upper surface of the dielectric layer and on the bottom surface of the opening is performed using a wet etch process.
7. The method of claim 1 , further comprising:
performing a chemical-mechanical planarizing (CMP) process to remove overburden portions of the layer of copper material, the seed layer, and the metallic liner layer, down to the portion of the first diffusion barrier layer on the upper surface of the dielectric layer;
recessing upper surfaces of the layer of copper material, the seed layer, and the metallic liner layer down to a level of the upper surface of the dielectric layer; and
performing a wet etch process to remove an overburden portion of the first diffusion barrier layer on the upper surface of the dielectric layer.
8. The method of claim 7 , wherein recessing the upper surfaces of the layer of copper material, the seed layer, and the metallic liner layer down to a level of the upper surface of the dielectric layer is performed using one or more wet etch processes.
9. The method of claim 7 , wherein recessing the upper surfaces of the layer of copper material, the seed layer, and the metallic liner layer down to a level of the upper surface of the dielectric layer is performed using a CMP process.
10. The method of claim 1 , wherein the dielectric layer comprises an interlayer dielectric (ILD) layer of a back-end-of-line (BEOL) structure.
11. The method of claim 1 , wherein the opening in the dielectric layer comprises a via opening which defines a via interconnect.
12. The method of claim 1 , wherein the opening in the dielectric layer comprises a trench opening which defines a wire interconnect.
13. The method of claim 1 , wherein the opening in the dielectric layer comprises a dual damascene opening which comprises a via opening and a trench opening disposed above the via opening.