Wafer dies with thermally conducting perimeter regions
A semiconductor structure includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
1 . A semiconductor structure comprising:
a first back-end-of-line region having a top surface and a bottom surface, the bottom surface of the first back-end-of-line region being coupled to a top surface of a front-end-of-line region;
a second back-end-of-line region having a top surface and a bottom surface, a top surface of the second back-end-of-line region being coupled to a bottom surface of the front-end-of-line region;
wherein the first back-end-of-line region has a first set of sidewalls extending from the top surface of the first back-end-of-line region to the bottom surface of the first back-end-of-line region;
wherein the front-end-of-line region has a second set of sidewalls extending from the top surface of the front-end-of-line region to the bottom surface of the front-end-of-line region;
wherein the second back-end-of-line region has a third set of sidewalls extending from the top surface of the second back-end-of-line region to the bottom surface of the second back-end-of-line region;
wherein the first set of sidewalls, the second set of sidewalls and the third set of sidewalls define a common outer perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region; and
a thermally conducting region disposed on:
(i) at least a portion of the first set of sidewalls of the first back-end-of line region;
(ii) at least a portion of the second set of sidewalls of the front-end-of-line region; and
(iii) at least a portion of the third set of sidewalls of the second back-end-of-line region.
2 . A semiconductor structure comprising:
a first back-end-of-line region coupled to a first side of a front-end-of-line region;
a second back-end-of-line region coupled to a second side of the front-end-of-line region;
a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region;
wherein the thermally conducting region comprises a thermally conducting material and a diffusion barrier layer, wherein the diffusion barrier layer separates the thermally conducting material from the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
3 . The semiconductor structure of claim 2 , wherein the thermally conducting region further comprises an oxide layer between the thermally conducting material and the front-end-of-line region.
4 . The semiconductor structure of claim 2 , wherein the thermally conducting region further comprises an oxide layer between (i) the thermally conducting material and (ii) the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
5 . The semiconductor structure of claim 2 , wherein the thermally conducting region comprises a copper material.
6 . The semiconductor structure of claim 2 , wherein the thermally conducting region comprises a thermally conducting material with a copper content of 80% or more.
7 . The semiconductor structure of claim 2 , further comprising one or more thermally conducting features positioned within the front-end-of-line region and extending through the second back-end-of-line region.
8 . The semiconductor structure of claim 2 , further comprising one or more thermally conducting features positioned within at least a portion of the first back-end-of-line region.
9 . The semiconductor structure of claim 2 , further comprising:
a first set of one or more thermally conducting features positioned within at least a portion of the first back-end-of-line region; and
a second set of one or more thermally conducting features positioned within at least a portion of the second back-end-of-line region.
10 . The semiconductor structure of claim 1 , wherein the first back-end-of-line region provides signal routing for one or more active devices in the front-end-of-line region, and wherein the second back-end-of-line region provides a power delivery structure for the one or more active devices in the front-end-of-line region.
11 . The semiconductor structure of claim 1 , wherein the first back-end-of-line region is coupled to a heat sink, and wherein the second back-end-of-line region is coupled to a packaging substrate.
12 . The semiconductor structure of claim 1 , wherein the thermally conducting region comprises a copper material.
13 . The semiconductor structure of claim 1 , wherein the thermally conducting region comprises a thermally conducting material with a copper content of 80% or more.
14 . The semiconductor structure of claim 1 , further comprising one or more thermally conducting features positioned within the front-end-of-line region and extending through the second back-end-of-line region.
15 . The semiconductor structure of claim 1 , further comprising one or more thermally conducting features positioned within at least a portion of the first back-end-of-line region.
16 . The semiconductor structure of claim 1 , further comprising:
a first set of one or more thermally conducting features positioned within at least a portion of the first back-end-of-line region; and
a second set of one or more thermally conducting features positioned within at least a portion of the second back-end-of-line region.
17 . The semiconductor structure of claim 2 , wherein the first back-end-of-line region provides signal routing for one or more active devices in the front-end-of-line region, and wherein the second back-end-of-line region provides a power delivery structure for the one or more active devices in the front-end-of-line region.
18 . The semiconductor structure of claim 2 , wherein the first back-end-of-line region is coupled to a heat sink, and wherein the second back-end-of-line region is coupled to a packaging substrate.