Semiconductor package having pads with stepped structure
A semiconductor package including a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a third semiconductor chip disposed on the second semiconductor chip. A first pad is disposed on a top surface of the second semiconductor chip, and includes a first portion and a second portion protruding in a vertical direction from the first portion. A width of the first portion in a first horizontal direction is greater than a width of the second portion in the first horizontal direction. A second pad is disposed on a bottom surface of the third semiconductor chip facing the top surface of the second semiconductor chip, and a solder ball is disposed as surrounding a sidewall of the second portion of the first pad between the first pad and the second pad.
1. A semiconductor package comprising:
a first semiconductor chip;
a second semiconductor chip on the first semiconductor chip;
a third semiconductor chip on the second semiconductor chip;
a first pad on a top surface of the second semiconductor chip, the first pad including a first portion and a second portion protruding in a vertical direction from the first portion, a width of the first portion in a first horizontal direction being greater than a width of the second portion in the first horizontal direction;
a second pad on a bottom surface of the third semiconductor chip, the bottom surface facing the top surface of the second semiconductor chip; and
a solder ball surrounding a sidewall of the second portion of the first pad between the first pad and the second pad.
2. The semiconductor package of claim 1 , wherein a thickness of the second portion of the first pad in the vertical direction is greater than a thickness of the first portion of the first pad in the vertical direction.
3. The semiconductor package of claim 2 , wherein the thickness of the first portion of the first pad in the vertical direction is 0.1 μm to 2 μm, and
the thickness of the second portion of the first pad in the vertical direction is 0.1 μm to 5 μm.
4. The semiconductor package of claim 1 , wherein the first pad further includes a first metal layer on a top surface of the second portion of the first pad.
5. The semiconductor package of claim 1 , wherein the second pad includes a first portion and a second portion protruding in the vertical direction from the first portion of the second pad, and
a width of the first portion of the second pad in the first horizontal direction is greater than a width of the second portion of the second pad in the first horizontal direction.
6. The semiconductor package of claim 5 , wherein the width of the second portion of the second pad in the first horizontal direction is the same as the width of the second portion of the first pad in the first horizontal direction.
7. The semiconductor package of claim 5 , wherein the first pad further includes a first metal layer on a top surface of the second portion of the first pad, and
the second pad further includes a second metal layer on a bottom surface of the second portion of the second pad.
8. The semiconductor package of claim 1 , wherein the second portion of the first pad is in contact with the second pad.
9. The semiconductor package of claim 8 , wherein the first pad further includes a first metal layer on a top surface of the second portion of the first pad and a second metal layer on a top surface of the first portion of the first pad, and
the second pad further includes a third metal layer on a bottom surface of the second pad.
10. The semiconductor package of claim 8 , further comprising:
an adhesive layer surrounding a sidewall of the first pad; and
an insulating layer surrounding at least a portion of a sidewall of the solder ball and a sidewall of the second pad.
11. The semiconductor package of claim 8 , wherein a width of the solder ball in the first horizontal direction is smaller than the width of the first portion of the first pad in the first horizontal direction.
12. The semiconductor package of claim 1 , wherein a width of the first portion of the first pad in a second horizontal direction perpendicular to the first horizontal direction is greater than a width of the second portion of the first pad in the second horizontal direction.
13. The semiconductor package of claim 1 , wherein a difference between the width of the first portion of the first pad in the first horizontal direction and the width of the second portion of the first pad in the first horizontal direction is 1 μm to 8 μm.
14. A semiconductor package comprising:
a first structure;
a second structure on the first structure;
a first pad on a top surface of the first structure, the first pad including a first portion and a second portion protruding in a vertical direction from the first portion, a width of the first portion in a first horizontal direction being greater than a width of the second portion in the first horizontal direction;
a second pad on a bottom surface of the second structure, the bottom surface facing the top surface of the first structure; and
a solder ball between the first pad and the second pad and surrounding a sidewall of the second portion of the first pad,
wherein the second portion of the first pad is in contact with the second pad, and
a width of the solder ball in the first horizontal direction is smaller than the width of the first portion of the first pad in the first horizontal direction.
15. The semiconductor package of claim 14 , further comprising:
a first semiconductor chip under the first structure,
wherein the first structure is a second semiconductor chip, and
the second structure is a third semiconductor chip.
16. The semiconductor package of claim 14 , further comprising a substrate under the first structure,
wherein the first structure is an interposer,
the second structure includes a first semiconductor chip and a second semiconductor chip spaced apart from the first semiconductor chip in the first horizontal direction, and
the first semiconductor chip is electrically connected to the second semiconductor chip through the first structure.
17. The semiconductor package of claim 14 , further comprising first and second semiconductor chips spaced apart from each other in the first horizontal direction on the second structure,
wherein the first structure is a substrate,
the second structure is an interposer, and
the first semiconductor chip is electrically connected to the second semiconductor chip through the second structure.
18. The semiconductor package of claim 14 , wherein the first structure is a first package including a first semiconductor chip, and the second structure is a second package including a second semiconductor chip.
19. The semiconductor package of claim 14 , wherein the first structure is a substrate, and the second structure is a semiconductor chip.
20. A semiconductor package comprising:
a first semiconductor chip;
a second semiconductor chip on the first semiconductor chip;
a third semiconductor chip on the second semiconductor chip;
a first pad on a top surface of the second semiconductor chip, the first pad including a first portion and a second portion protruding in a vertical direction from the first portion, a width of the first portion in a first horizontal direction being greater than a width of the second portion in the first horizontal direction, a width of the first portion in a second horizontal direction perpendicular to the first horizontal direction being greater than a width of the second portion in the second horizontal direction;
a second pad on a bottom surface of the third semiconductor chip, the bottom surface facing the top surface of the second semiconductor chip;
a first solder ball on a bottom surface of the first semiconductor chip;
a second solder ball between the first pad and the second pad, and surrounding a sidewall of the second portion of the first pad;
a through via penetrating the second semiconductor chip in the vertical direction and connected to the first pad; and
an adhesive layer between the second semiconductor chip and the third semiconductor chip, and surrounding a sidewall of each of the first pad, the second pad, and the second solder ball,
wherein a thickness of the second portion of the first pad in the vertical direction is greater than a thickness of the first portion of the first pad in the vertical direction,
a thickness of the first portion of the first pad in the vertical direction is 0.1 μm to 2 μm, and
a thickness of the second portion of the first pad in the vertical direction is 0.1 μm to 5 μm.