3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport

1. A method of fabricating a thin wafer die, the method comprising the steps of:

creating circuits and front-end-of-line wiring on a silicon wafer;

drilling holes in a topside of said silicon wafer;

depositing an insulator on said drilled holes surface to provide a dielectric insulator to the silicon;

removing any excess surface deposition from the surface;

putting a metal fill into said holes to form through-silicon-vias (TSV);

creating back-end-of-line wiring and pads on the top surface for interconnection;

attaching a glass handle to the wafer with a temporary adhesive;

thinning down the wafer to expose the insulator in from the TSVs, wherein said TSVs are adapted to be contacted from a backside of said wafer;

depositing an insulating layer which contacts said TSV dielectric;

thinning down the backside of said silicon wafer;

opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon; and

depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer,

wherein an integrated circuit is formed on said wafer.

2. The method of claim 1 , further comprising forming solder connections between the thinned silicon layers from said solder bumps and said ball limiting metallurgy pads, wherein an integrated circuit is formed between die from multiple wafers.

3. The method of claim 1 , wherein said holes are drilled with a deep reactive ion etch (DRIE).

4. The method of claim 1 , wherein said top surface insulator is removed by a chemical-mechanical polish (CMP).

5. The method of claim 1 , wherein said metal fill comprises a barrier, an adhesive, and a conductor.

6. The method of claim 5 , wherein said metal fill comprises one of Titanium-Titanium Nitride-Tungsten (Ti—TiN—W), Tantalum-Tantalum Nitride-Tungsten (Ta—TaN—W), Titanium-Titanium Nitride-Copper (Ti—TiN—Cu), and Tantalum-Tantalum Nitride-Copper (Ta—TaN—Cu).

7. The method of claim 1 , wherein said back-end-of-line pads are ball limiting metallurgy (BLM) pads and said interconnections are formed from solder.

8. The method of claim 1 , wherein said glass handle wafer is attached by means of grinding, polishing, and a reactive ion etch.

9. The method of claim 1 , wherein said insulating layer is one or more of a plasma-enhanced chemical vapor deposition (PECVD) oxide layer and a nitride layer.

10. A method of fabricating a thin wafer die, the method comprising the steps of:

creating circuits and front-end-of-line wiring on a silicon wafer;

creating at least a portion of back-end-of-line wiring and pads on a top surface of said wafer for interconnection;

drilling holes in said top surface of said silicon wafer;

depositing an insulator on said drilled holes surface to provide a dielectric insulator to the silicon;

removing any excess surface deposition from the surface;

putting a metal fill into said holes to form through-silicon-vias (TSVs);

completing the creation of said larger back end of line wiring and surface pads, if not already completed;

attaching a glass handle to said silicon wafer with temporary adhesive;

thinning down the wafer to expose the insulator in from the TSV's, wherein said TSVs are adapted to be contacted from a backside of said wafer;

depositing an insulating layer such as PECVD oxide and/or nitride layer which contacts said TSV dielectric;

thinning down the backside of said silicon wafer;

opening through the dielectric to expose the conductor of the TSV to provide dielectric insulation about the exposed backside of said silicon wafer;

depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer; and

forming solder connections between the thinned silicon layers from said solder bumps and said ball limiting metallurgy pads, wherein an integrated circuit is formed between die from multiple wafers.