Semiconductor device including stress control layer and methods of forming the same
A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the top die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least −100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.
1 . A semiconductor device comprising:
a bottom die comprising:
a first semiconductor layer; and
a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer and electrically interconnecting components of the first semiconductor layer;
a top die disposed on a top surface of the first semiconductor layer, the top die comprising:
a second semiconductor layer; and
a second RDL disposed on the top surface of the first semiconductor layer and electrically interconnecting components of the second semiconductor layer;
a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the top die; and
a dielectric layer disposed on the SC layer,
wherein at room temperature,
the SC layer is configured to apply a compressive stress of at least −100 mega Pascals (MPa) to the top surface of the first semiconductor layer, or
the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.
2 . The semiconductor device of claim 1 , wherein the first semiconductor layer has a thickness less than or equal to 100 microns (μm) and a length to width aspect ratio of two or more.
3 . The semiconductor device of claim 2 , further comprising an interposer bonded to a bottom surface of the first RDL,
wherein the SC layer is configured to planarize the first semiconductor layer during bonding of the first RDL to the interposer, such that a distance between the first RDL and the interposer, taken in a vertical direction perpendicular to the top surface of the first semiconductor layer, varies by 2 μm or less.
4 . The semiconductor device of claim 3 , wherein the distance varies by 1 μm or less.
5 . The semiconductor device of claim 1 , wherein the SC layer has a thickness ranging from about 1000 angstroms to about 20,000 angstroms.
6 . The semiconductor device of claim 1 , wherein the SC layer and the dielectric layer generate different amounts of residual stress.
7 . The semiconductor device of claim 1 , wherein:
the SC layer is configured to apply a tensile stress of at least 200 MPa to the top surface of the first semiconductor layer; and
the first RDL is configured to apply a tensile stress to the bottom surface of the first semiconductor layer.
8 . The semiconductor device of claim 1 , wherein:
the SC layer is configured to apply a compressive stress of at least −200 MPa to the top surface of the first semiconductor layer; and
the first RDL is configured to apply a compressive stress to the bottom surface of the first semiconductor layer.
9 . The semiconductor device of claim 1 , wherein, at temperatures ranging from 220° C. to 250° C., an amount of residual stress applied to the first semiconductor layer by the SC layer is within +/−10% of an amount of residual stress applied to the first semiconductor layer by the first RDL.
10 . A semiconductor device comprising:
a bottom die comprising:
a first semiconductor layer; and
a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer and electrically interconnecting components the first semiconductor layer;
a stress control (SC) layer disposed on a top surface of the first semiconductor layer;
a dielectric layer disposed on the SC layer; and
an interposer bonded to a bottom surface of the first RDL,
wherein at room temperature,
the SC layer is configured to apply a compressive stress of at least −100 mega Pascals (MPa) to the top surface of the first semiconductor layer; or
the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.
11 . The semiconductor device of claim 10 , wherein the first semiconductor layer has a thickness of 100 microns (μm) or less and a length to width aspect ratio of two or more.
12 . The semiconductor device of claim 11 , wherein the SC layer is configured to planarize the first semiconductor layer during bonding of the first RDL to the interposer, such that a distance between the first RDL and the interposer, taken in a vertical direction perpendicular to the top surface of the first semiconductor layer, varies by 2 μm or less.
13 . The semiconductor device of claim 12 , wherein the distance varies by 1 μm or less.
14 . The semiconductor device of claim 10 , wherein:
the dielectric layer comprises silicon oxide (SiO x ); and
the SC layer comprises silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon-germanium (Si 1-x Ge x ), tungsten (W), or silicon carbide (SiC), and the SC layer has a thickness ranging from about 10 nanometers (nm) to about 20,000 nm.
15 . The semiconductor device of claim 10 , wherein:
the SC layer is configured to apply a compressive stress of at least −200 mega Pascals (MPa) to the top surface of the first semiconductor layer; and
the first RDL is configured to apply a compressive stress to the bottom surface of the first semiconductor layer.
16 . The semiconductor device of claim 10 , wherein:
the SC layer is configured to apply a tensile stress of at least 200 MPa to the top surface of the first semiconductor layer; and
the first RDL is configured to apply a tensile stress to the bottom surface of the first semiconductor layer.
17 . A method of forming a semiconductor device, comprising:
bonding top dies to a top surface of a bottom die;
depositing a stress control (SC) layer on top and side surfaces of the top dies and on the top surface of the bottom die;
depositing a dielectric layer on the SC layer to form an intermediate structure;
planarizing the intermediate structure to expose top surfaces of the top dies; and
reflow bonding an interposer to a bottom surface of the bottom die,
wherein at room temperature:
the SC layer is configured to apply a compressive stress of at least −100 mega Pascals (MPa) to the top surface of the bottom die; or
the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the bottom die.
18 . The method of claim 17 , wherein:
the dielectric layer comprises silicon oxide (SiO x ); and
the SC layer comprises silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon-germanium (Si 1-x Ge x ), tungsten (W), or silicon carbide (SiC), and the SC layer has a thickness ranging from about 10 nanometers (nm) to about 20,000 nm.
19 . The method of claim 18 , wherein:
the reflow bonding comprises heating at a bonding temperature ranging from 220° C. to 250° C.; and
the SC layer is configured to planarize the bottom die during the reflow bonding, such that a distance between the bonding pads of the bottom die and bonding pads of the interposer, taken in a vertical direction perpendicular to the top surface of the lower die, varies by 2 μm or less.
20 . The method of claim 18 , wherein the bonding top dies to a top surface of a bottom die comprises face-to-face bonding or face-to-back bonding of the top dies to the bottom die.