IP Library Granted Patent US 9,768,071
Granted Patent B2
US 9,768,071 · App. 15/159,259 · Granted Sep 19, 2017

Asymmetric high-K dielectric for reducing gate induced drain leakage

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Quick Facts
Patent No.
US 9,768,071
App. No.
15/159,259
Granted
Sep 19, 2017
Kind
B2
Abstract

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Claims (20)

1. A method, comprising:

performing a blocking process on a high-k dielectric material on a source side of a gate structure; and

performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on the source side of the gate structure adjacent to a source region,

wherein the blocking process comprises a formation of a nitride sidewall on the high-k dielectric material on the source side of a gate structure, and

wherein the blocking process comprises damaging a nitride sidewall on the drain side of the gate structure.

2. The method of claim 1 , wherein the oxide on the source side remains the same during the oxygen annealing process.

3. The method of claim 1 , wherein an angled oxygen implant is performed after spacer formation.

4. The method of claim 1 , further comprising applying a RIE process on the drain side to create a poor encapsulation to enhance regrowth.

5. The method of claim 1 , wherein the gate structure is formed by a gate first process.

6. The method of claim 5 , wherein the gate first process is performed in finFET technologies.

7. The method of claim 1 , wherein the gate structure is formed with a high-k dielectric gate material.

8. The method of claim 7 , further comprising forming an intervening interfacial layer between the high-k dielectric gate material and an underlying substrate.

9. The method of claim 1 , wherein the blocking process comprising forming a mask on the source side, followed by an angled implant of damaging species to damage the nitride sidewall on the drain side.

10. The method of claim 9 , wherein the damaging species is one of oxygen, Germanium, Xenon and Argon on the drain side.

11. The method of claim 9 , wherein the damaging species is an etchant used with reactive ion etching processes on the drain side.

12. The method of claim 9 , further comprising removing the mask followed by a regrowth of oxygen.

13. The method of claim 12 , wherein the removing the mask is performed by a dry process using N 2 H 2 or a wet process.

14. The method of claim 13 , wherein the regrowth of oxygen is formed on a drain side of the gate structure.

15. The method of claim 14 , wherein the regrowth of oxygen is formed adjacent the drain region during a low temperature annealing process.

16. The method of claim 15 , wherein a halo and extension implant process is performed after spacer formation.

Assignments (3)
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2016
From: CHOU, ANTHONY I.; KUMAR, ARVIND; LIN, CHUNG-HSUN; NARASIMHA, SHREESH; ORTOLLAND, CLAUDE; SHAW, JONATHAN T.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038651/0430 →