Very planar gate cut post replacement gate process
A semiconductor structure with improved gate planarity and method of fabrication are provided. In a replacement gate scheme, an array of sacrificial gate structures of substantially uniform pitch and spacing formed over a semiconductor substrate is removed and replaced with functional gate structures. Portions of functional gate structures that are accounted as extraneous features in a circuit design are subsequently removed and the removed portions of the functional gate structures are filled with a dielectric material. Because the functional gate structures of substantially uniform pitch and spacing are formed before removal of unwanted portions of the functional gate structures, the chemical mechanical polishing process can be accomplished uniformly across the semiconductor substrate. The functional gate structures thus formed have a substantially uniform height across the substrate.
1. A method of forming a semiconductor structure comprising:
forming an array of functional gate structures of substantially uniform pitch and spacing over a semiconductor substrate, wherein the functional gate structures are of a substantially uniform height, and wherein the functional gate structures are separated from each other by first dielectric material layer portions;
removing portions of the functional gate structures according to a circuit design to form openings in the functional gate structures, wherein the openings extend through the functional gate structures to expose a top surface of the semiconductor substrate; and
forming second dielectric material layer portions in the openings.
2. The method of claim 1 , wherein the removed portions of the functional gate structures are extraneous features in the circuit design.
3. The method of claim 1 , wherein the semiconductor substrate is a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.
4. The method of claim 1 , wherein each of the functional gate structures comprises a gate dielectric material portion, a work function metal material portion, and a conductive material portion.
5. The method of claim 4 , wherein the gate dielectric material portion comprises HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , SiON, SiN X , a silicate thereof, or an alloy thereof.
6. The method of claim 4 , wherein the work function metal material portion comprises TiN, TiSiN, TaN, TaSiN, TiTaN, TaRuN, WN, WSiN, or combinations thereof.
7. The method of claim 4 , wherein the conductive material portion comprises Al, W, Cu, Pt, Ag, Au, Ru, Ir, Rh, Re, alloys thereof, or silicides thereof.
8. The method of claim 1 , wherein the first dielectric material layer portions comprises silicon oxide.
9. The method of claim 1 , wherein the second dielectric material layer portions comprises silicon nitride.
10. The method of claim 1 , wherein the forming of said array of functional gate structures of said substantially uniform pitch and spacing over said semiconductor substrate comprises:
forming an array of sacrificial gate structures of substantially uniform pitch and spacing over the semiconductor substrate;
forming a first dielectric material layer over the sacrificial gate structures, the first dielectric material layer filling spaces between the sacrificial gate structures;
performing a chemical mechanical polishing (CMP) process on the first dielectric material layer to expose the sacrificial gate structures and to provide the first dielectric material layer portions filling spaces between the sacrificial gate structures;
removing the sacrificial gate structures to reveal gate cavities; and
forming the functional gate structures in the gate cavities.
11. The method of claim 10 , wherein the forming of said array of functional gate structures of said substantially uniform pitch and spacing over said semiconductor substrate further comprises:
depositing blanket layers of a material stack of a gate dielectric material, a work function metal material, and a conductive material over the first dielectric material portions and in the gate cavities; and
performing another CMP process to remove the gate dielectric material, the work function metal material, and the conductive material outside of the gate cavities and to provide a gate dielectric material portion, a work function metal material portion, and a conductive material portion in each gate cavity.
12. The method of claim 1 , wherein the forming of said array of sacrificial gate structures of substantially uniform pitch and spacing over said semiconductor substrate comprises:
depositing a blanket layer of a disposable gate material layer; and
patterning the blanket layer of the disposable gate material layer to form the sacrificial gate structures of substantially uniform pitch and spacing.
13. The method of claim 12 further comprising forming a plurality of semiconductor fins prior to the depositing the blanket layer of a disposable gate material layer.
14. The method of claim 1 , wherein the forming second dielectric material layer portions in the removed portions of the functional gate structures comprises:
forming a second dielectric material layer over the functional gate structures and the first dielectric material layer portions, the second dielectric material layer filling the removed portions of the functional gate structures; and
recessing the second dielectric material layer to expose the functional gate structures and the first dielectric material layer portions by CMP or etching.
15. A method of forming a semiconductor structure comprising:
forming an array of functional gate structures of substantially uniform pitch and spacing over a semiconductor substrate, wherein the functional gate structures are of a substantially uniform height, and wherein the functional gate structures are separated from each other by first dielectric material layer portions;
removing portions of the functional gate structures according to a circuit design, wherein the removing portions of the functional gate structures according to said circuit design comprises:
forming a photoresist layer overlying the functional gate structures and the first dielectric material layer portions;
forming openings in the photoresist layer, the openings exposing portions of the functional gate structures that represent extraneous features in the circuit design; and
removing the exposed portions of the functional gate structures; and
forming second dielectric material layer portions in the removed portions of the functional gate structures.
16. A semiconductor structure comprising:
first dielectric material layer portions arranged in a uniform array and extending in a first direction across a semiconductor substrate;
a plurality of functional gate structures disposed in portions of spaces between the first dielectric material layer portions, the functional gate structures having a substantially uniform height; and
second dielectric material layer portions disposed in remaining portions of the spaces between the first dielectric material layer portions,
wherein the plurality of functional gate structures are separated from each other by the first dielectric material layer portions in the first direction, and
wherein ends of portions of the plurality of functional gate structures are separated from each other by the second dielectric material layer portions in a second direction perpendicular to the first direction, the second dielectric material layer portions having a same width as the adjoined portions of the plurality of functional gate structures.
17. The semiconductor structure of claim 16 , wherein the semiconductor substrate is a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.
18. The semiconductor structure of claim 16 , wherein the first dielectric material layer portions comprises silicon oxide.
19. The semiconductor structure of claim 16 , wherein the second dielectric material layer portions comprises silicon nitride.
20. The semiconductor structure of claim 16 , wherein each of the plurality of functional gate structures comprises a gate dielectric material portion, a work function metal material portion, and a conductive material portion.