Fin cut without residual fin defects
View Patent ↗A method of forming semiconductor fins is provided. Sacrificial fins are provided on a surface of substrate. A hard mask layer, formed around the sacrificial fins and the gaps therebetween, is made coplanar with a topmost surface of the sacrificial fins. A fin cut mask then covers a portion of the sacrificial fins and partly covers a sacrificial fin. Trenches are formed in the hard mask layer by removing sacrificial fins not covered by the fin cut mask and that portion of the sacrificial fin not partly covered by the fin cut mask. Spacers are formed on the sidewalls of the trenches and a plug is formed in the trench formed by removing that portion of the sacrificial fin not partly covered by the fin cut mask. Semiconductor fins are grown epitaxially in the trenches having the spacers from the exposed surface of the substrate upward.
1. A method of forming semiconductor fins comprising:
providing an array of sacrificial fins having gaps therebetween on a surface of semiconductor substrate;
forming a hard mask layer on the surface of the sacrificial fins and in the gaps;
providing a fin cut mask on the hard mask layer to cover a portion of the sacrificial fins and partly cover at least one sacrificial fin;
forming trenches in the hard mask to expose the surface of the semiconductor substrate by selectively removing the sacrificial fins not covered by the fin cut mask and by selectively removing the portion of the at least one sacrificial fin not partly covered by the fin cut mask;
removing the fin cut mask and forming spacers on the sidewalls of the trenches and forming a plug in the trench formed by the removal of the portion of the at least one sacrificial fin not partly covered by the fin cut mask; and
growing semiconductor fins in the trenches having the spacers on the sidewalls from the exposed surface of the semiconductor substrate upward.
2. The method of claim 1 , further comprising planarizing the hard mask layer until coplanar with a topmost surface of the sacrificial fins prior to providing the fin cut mask.
3. The method of claim 2 , wherein the planarizing step comprises chemical mechanical polishing (CMP).
4. The method of claim 1 , further comprising:
recessing the hard mask layer, the spacers, and the plug, to expose the topmost surface of the grown semiconductor fins.
5. The method of claim 4 , further comprising:
forming a functional gate structure over a portion of at least one entirely exposed grown semiconductor fin.
6. The method of claim 1 , further comprising:
removing the hard mask layer, the sacrificial fins that were covered by the fin cut mask, the spacers, and the plug, to entirely expose the grown semiconductor fins.
7. The method of claim 6 , wherein the hard mask layer, the sacrificial fins that were covered by the fin cut mask, the spacers, and the plug, are removed by a reactive ion etch or a chemical etch.
8. The method of claim 1 , wherein the fin cut mask is a photoresist of inverse polarity.
9. The method of claim 1 , wherein the trench formed by selectively removing the portion of the at least one sacrificial fin not partly covered by the fin cut mask is formed by a directional etch.
10. The method of claim 1 , wherein the spacers are formed on the sidewalls of the trenches by atomic layer deposition (ALD) followed by a selective etching process to expose the surface of the substrate.
11. The method of claim 10 , wherein the selective etching process is anisotropic reactive ion etch (RIE).
12. The method of claim 1 , wherein the semiconductor fins are grown epitaxially.
13. The method of claim 1 , wherein the fin cut mask is removed by plasma ashing.
14. The method of claim 1 , wherein the spacers on the sidewalls of the trenches have a thickness of between about 3 nm to about 10 nm.