IP Library Granted Patent US 9,779,944
Granted Patent B1
US 9,779,944 · App. 15/263,959 · Granted Oct 3, 2017

Method and structure for cut material selection

Inventors: Sean D. Burns (Hopewell Junction, NY); Lawrence A. Clevenger (LaGrangeville, NY); Matthew E. Colburn (Schenectady, NY); Nelson M. Felix (Briarcliff Manor, NY); Sivananda K. Kanakasabapathy (Niskayuna, NY); Yann A. M. Mignot (Slingerlands, NY); Christopher J. Penny (Saratoga Springs, NY); Roger A. Quon (Rhinebeck, NY); Nicole A. Saulnier (Albany, NY)
Assignee: International Business Machines Corporation
H01L21/0338H01L21/0337H01L21/31144
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Quick Facts
Patent No.
US 9,779,944
App. No.
15/263,959
Granted
Oct 3, 2017
Kind
B1
Abstract

A method for manufacturing a semiconductor device includes forming a plurality of mandrels on a dielectric layer, conformally depositing a spacer layer on the plurality of mandrels, removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels, removing the at least one of the plurality of mandrels to create at least one opening, and filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer.

Claims (59)

1. A method for manufacturing a semiconductor device, comprising:

forming a plurality of mandrels on a dielectric layer;

conformally depositing a spacer layer on the plurality of mandrels;

removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels;

removing the at least one of the plurality of mandrels to create at least one opening;

filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer; and

forming a hardmask layer between the dielectric layer and the plurality of mandrels.

2. The method according to claim 1 , wherein the material of the spacer layer and the cut fill material comprise at least one of silicon dioxide (SiO 2 ), or another material such as, for example, silicon nitride (SiN), siliconborocarbonitride (SiBCN) or titanium dioxide (TiO 2 ).

3. The method according to claim 1 , further comprising selectively etching a portion of the hardmask layer simultaneously with respect to the spacer layer and the cut fill material.

4. A method for manufacturing a semiconductor device, comprising:

forming a plurality of mandrels on a dielectric layer;

conformally depositing a spacer layer on the plurality of mandrels;

removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels;

removing the at least one of the plurality of mandrels to create at least one opening;

filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer;

depositing an organic fill material in the at least one opening and around a remaining portion of the spacer layer prior to filling the at least one opening with the cut fill material; and

removing the organic fill material from the at least one opening.

5. The method according to claim 4 , further comprising stripping a remainder of the organic fill material.

6. A method for manufacturing a semiconductor device, comprising:

forming a plurality of mandrels on a dielectric layer;

conformally depositing a spacer layer on the plurality of mandrels;

removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels;

removing the at least one of the plurality of mandrels to create at least one opening;

filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer; and

depositing an organic fill material on the conformally deposited spacer layer prior to removing the portion of the spacer layer from the top surface of the at least one of the plurality of mandrels.

7. The method according to claim 6 , further comprising:

patterning the organic fill material to create an opening in the organic fill material exposing the portion of the spacer layer on the top surface of the at least one of the plurality of mandrels.

8. The method according to claim 7 , further comprising filling the opening in the organic fill material with the cut fill material.

9. The method according to claim 8 , further comprising:

patterning the organic fill material to create another opening in the organic fill material exposing another portion of the spacer layer; and

filling the other opening in the organic fill material with additional cut fill material.

10. The method according to claim 9 , wherein the additional cut fill material comprises the same material as a material of the spacer layer and the cut fill material.

11. The method according to claim 10 , further comprising:

removing a portion of the cut fill material and a portion of the additional cut fill material to expose the organic fill material; and

selectively removing the organic fill material simultaneously with respect to a remaining portion of the spacer layer, the cut fill material and the additional cut fill material.

12. A method for manufacturing a semiconductor device, comprising:

forming a hardmask layer on a dielectric layer;

depositing an organic layer on the hardmask layer;

patterning the organic layer into a plurality of mandrels;

conformally depositing a spacer layer on the plurality of mandrels;

removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels;

removing the at least one of the plurality of mandrels to create at least one opening;

filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer; and

selectively etching a portion of the hardmask layer simultaneously with respect to the spacer layer and the cut fill material.

13. The method according to claim 12 , further comprising:

depositing an organic fill material in the at least one opening and around a remaining portion of the spacer layer prior to filling the at least opening with the cut fill material; and

removing the organic fill material from the at least one opening.

14. The method according to claim 13 , further comprising stripping a remainder of the organic fill material.

15. The method according to claim 12 , further comprising:

depositing an organic fill material on the conformally deposited spacer layer prior to removing the portion of the spacer layer from the top surface of the at least one of the plurality of mandrels.

16. The method according to claim 15 , further comprising:

patterning the organic fill material to create an opening in the organic fill material exposing the portion of the spacer layer on the top surface of the at least one of the plurality of mandrels.

17. The method according to claim 16 , further comprising filling the opening in the organic fill material with the cut fill material.

18. A method for manufacturing a semiconductor device, comprising:

forming a plurality of mandrels spaced apart from each other on a dielectric layer;

conformally depositing a spacer layer on the plurality of mandrels, wherein the spacer layer occupies a portion of each of a plurality of gaps between adjacent mandrels;

depositing an organic fill material on the spacer layer, wherein the organic fill material blocks one or more of the plurality of gaps; and

depositing a cut fill material in a remaining portion of one or more exposed gaps of the plurality of gaps, wherein the cut fill material comprises the same material as a material of the spacer layer.

19. The method according to claim 18 , further comprising stripping the organic fill material.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0771 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0868 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2016
From: BURNS, SEAN D.; CLEVENGER, LAWRENCE A.; COLBURN, MATTHEW E.; FELIX, NELSON M.; KANAKASABAPATHY, SIVANANDA K.; MIGNOT, YANN A.M.; PENNY, CHRISTOPHER J.; QUON, ROGER A.; SAULNIER, NICOLE A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040019/0688 →