Asymmetric finFET memory access transistor

1. A field effect transistor device, comprising:

a semiconductor substrate;

a doped source layer arranged on the semiconductor substrate;

an insulator layer arranged on the doped source layer;

a fin arranged on the insulator layer;

a source region extension portion extending from the doped source layer and through the fin;

a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion;

a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.

2. The device of claim 1 , wherein a dopant concentration of the doped source layer is greater than the graduated doping concentration of the drain region.

3. The device of claim 1 , wherein the source region extension portion includes a doped semiconductor material.

4. The device of claim 1 , wherein the fin includes a semiconductor portion and a nitride portion.

5. The device of claim 1 , wherein the insulator layer is arranged about the source region extension portion.

6. A field effect transistor device, comprising:

a semiconductor substrate;

a doped source layer arranged on the semiconductor substrate;

an insulator layer arranged on the doped source layer;

a fin arranged in contact with the insulator layer;

a source region extension portion extending from the doped source layer and through the fin;

a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion;

a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.