Low resistance metal contacts to interconnects
View Patent ↗A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact.
1. A semiconductor device, comprising:
a dielectric layer formed on a semiconductor layer;
a contact fabricated in a via formed within the dielectric layer; and
an interconnect formed entirely above the contact to interface with an exposed surface of the contact opposite a surface closest to the semiconductor layer, wherein the contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact, the first portion is greater than the second portion, and the interface metal includes one or more of: cobalt, nickel, palladium, platinum, and ruthenium, wherein the via comprises only the contact material and the interface metal.
2. The device according to claim 1 , wherein the exposed surface of the contact includes both the first portion of the contact and the second portion of the contact.
3. The device according to claim 1 , wherein the exposed surface of the contact includes only the second portion of the contact which includes the interface metal.
4. The device according to claim 1 , wherein the contact material includes tungsten.
5. The device according to claim 1 , wherein the second portion of the contact which includes the interface metal forms an opening within the first portion which includes the contact material.
6. The device according to claim 1 , wherein the first portion forms a lining on a wall of the via and on a surface of the dielectric layer opposite the exposed surface.
7. The device according to claim 1 , wherein the second portion is in a seam within the first portion.
8. The device according to claim 1 , wherein the second portion is formed as a cap over the first portion.
9. The device according to claim 1 , wherein two or more of the contacts fabricated in respective vias are adjacent and are about 20 to 70 nanometers apart from center-to-center.
10. The device according to claim 1 , further comprising a low-k dielectric layer formed above the dielectric layer in which the contacts are formed.
11. The device according to claim 1 , further comprising a nitride cap conformally formed over the interconnect.