Copper interconnect structures
View Patent ↗Semiconductor devices include a patterned dielectric layer overlaying a semiconductor substrate; a metal layer comprising copper disposed in the patterned dielectric layer; and a barrier layer formed at an interface between the dielectric layer and the metal layer, wherein the barrier layer is AlOxNy. The patterned dielectric may define a trench and via interconnect structure or first and second trenches for a capacitor structure. Also disclosed are processes for forming the semiconductor device, which includes subjecting the dielectric surfaces to a nitridization process to form a nitrogen enriched surface. Aluminum metal is then conformally deposited onto the nitrogen enriched surfaces to form AlOxNy at the aluminum metal/dielectric interface. The patterned substrate is then metalized with copper and annealed. Upon annealing, a copper aluminum alloy is formed at the copper metal/aluminum interface.
1. A method for forming a semiconductor device comprising:
providing a patterned substrate comprising a trench structure and a via structure in a dielectric layer;
exposing the surfaces of the trench and via structures with nitrogen ions to form a nitrogen enriched surface on and/or in a portion of the dielectric layer defining the trench and via structures;
conformally depositing an aluminum metal layer onto the exposed surfaces of the trench and via structures in the presence of oxygen species in the dielectric to form an aluminum oxynitride liner layer with the nitrogen ions within the nitrogen enriched surface;
depositing a copper metal into the trench and via structures; and
annealing to form a copper aluminum alloy at an interface of the copper metal and the aluminum metal layer.
2. The method of claim 1 , wherein the nitrogen ions are generated from a nitrogen containing gas by exposing the nitrogen containing gas to an energy source effective to generate the nitrogen ions from the nitrogen containing gas.
3. The method of claim 1 , wherein the energy source is a plasma energy source.
4. The method of claim 1 , wherein the energy source is a thermal energy source.
5. The method of claim 1 , wherein the dielectric layer is an interlevel dielectric layer.
6. A method for forming a semiconductor device comprising:
providing a patterned substrate comprising a trench structure and a via structure in a dielectric layer, wherein the dielectric layer is formed on a capping layer overlying a copper conductor, wherein the trench and via structure exposes a surface of the metal conductor;
exposing the patterned substrate with nitrogen ions to form a nitrogen enriched surface on and/or in a portion of the dielectric layer defining the trench and via structures;
conformally depositing an aluminum metal layer onto the nitrogen enriched surfaces of the trench and via structures in the presence of oxygen species in the dielectric to form an aluminum containing liner layer on and in the nitrogen enriched dielectric surfaces of the trench and via structures;
depositing a copper metal into the trench and via structures; and
annealing to form a copper aluminum alloy at an interface of the copper conductor and the aluminum metal layer.
7. The method of claim 6 , wherein the aluminum containing liner layer on and in the exposed dielectric surfaces of the trench and via structures is an aluminum oxynitride.
8. The method of claim 6 , wherein the aluminum metal layer is at a thickness within a range of 0.5 Angstroms to 250 Angstroms.
9. The method of claim 6 , wherein the aluminum containing liner layer on and in the exposed dielectric surfaces of the trench and via structures is an aluminum oxide.
10. The method of claim 6 , wherein the nitrogen ions are generated from a nitrogen containing gas by exposing the nitrogen containing gas to an energy source effective to generate the nitrogen ions from the nitrogen containing gas.
11. The method of claim 10 , wherein the energy source is a plasma energy source.
12. The method of claim 10 , wherein the energy source is a thermal energy source.
13. The method of claim 6 , wherein the annealing is at a temperature within a range of 100° C. to 300° C. for a period ranging from 10 minutes to 60 minutes.
14. The method of claim 6 , wherein the dielectric layer is an interlevel dielectric layer.
15. The method of claim 6 , wherein the capping layer comprises silicon nitride, silicon carbide, silicon oxycarbide, hydrogenated silicon carbide, silicon dioxide, or organosilicate glass.