Fin cut on sit level
View Patent ↗A method of forming semiconductor fins with variable pitches of arbitrary values in a sidewall image transfer (SIT) process is provided. After forming an array of first mandrel structures with a constant pitch and removing at least one first mandrel structure form the array, a set of second mandrel structures are formed overlapping the first mandrel structures. The combination of the first mandrel structures and the second mandrel structures defines pitches of sidewall spacer patterns to be subsequently formed.
1. A semiconductor structure comprising a plurality of semiconductor fins located on a substrate, each of the plurality of semiconductor fins having a same width, wherein:
a first sub-set of the plurality of semiconductor fins have a first pitch equal to a sum of the width of one semiconductor fin in the plurality of semiconductor fins and a spacing between two closest adjacent semiconductor fins in the first sub-set of the plurality of semiconductor fins,
a second sub-set of the plurality of semiconductor fins have a second pitch equal to n times the first pitch, wherein n is an integer from 3 to 9, and
a third sub-set of the plurality of semiconductor fins have a third pitch greater than a first pitch, wherein the third pitch does not equal to an integer multiplication of the first pitch.
2. The semiconductor structure of claim 1 , wherein the width of each of the plurality of the semiconductor fins ranges from 5 to 50 nm.
3. The semiconductor structure of claim 1 , wherein the first pitch is from 10 to 50 nm.
4. The semiconductor structure of claim 1 , wherein each of the plurality of the semiconductor fins comprises silicon, germanium, a silicon-germanium alloy, a silicon-carbon alloy, a III-V compound semiconductor material or a II-VI compound semiconductor material.
5. The semiconductor structure of claim 1 , wherein each of the plurality of the semiconductor fins has a height from 5 nm to 300 nm.
6. The semiconductor structure of claim 1 , wherein the substrate comprises an insulator layer located over a handle substrate, wherein the plurality of the semiconductor fins protrudes from a top surface of the insulator layer.
7. The semiconductor structure of claim 6 , wherein the insulator layer comprises silicon oxide.
8. The semiconductor structure of claim 6 , wherein the handle substrate comprises silicon, germanium, a silicon-germanium alloy, a silicon-carbon alloy, a III-V compound semiconductor material or a II-VI compound semiconductor material.
9. The semiconductor structure of claim 6 , wherein the insulator layer is a single continuous layer that spans an entirety of the handle substrate.
10. The semiconductor structure of claim 6 , wherein the insulator layer has a discontinuous structure comprising isolated islands separated by a semiconductor material.
11. The semiconductor structure of claim 6 , wherein the insulator layer has a thickness from 50 nm to 5 microns.