Fin cut during replacement gate formation
View Patent ↗A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
1. A method of forming a semiconductor structure, the method comprising:
depositing a dielectric over a plurality of fins;
applying a mask only over a first portion of the plurality of fins to define a second portion of the plurality of fins that are exposed by the mask including all fins to be cut;
employing the mask to remove the dielectric from the second portion of the plurality of fins including all fins to be cut;
depositing a replacement gate stack over the first and second portions of the plurality of fins; and
removing the second portion of the plurality of fins including all fins to be cut during etching of the replacement gate stack.
2. The method of claim 1 , wherein removal of the fins to be cut results in recesses formed within a semiconductor layer receiving the plurality of fins.
3. The method of claim 2 , further comprising depositing a spacer within the recesses formed by the removal of the fins to be cut.
4. The method of claim 3 , wherein the spacer is a non-conducting dielectric layer.
5. The method of claim 1 , wherein the replacement gate stack includes a dummy gate and a gate hard mask.
6. The method of claim 5 , wherein the dummy gate is formed of amorphous silicon.
7. The method of claim 1 , wherein the mask is an organic planarization layer (OPL).
8. The method of claim 1 , wherein each of the plurality of fins is formed by silicon (Si).
9. The method of claim 1 , wherein each of the plurality of fins is formed by silicon germanium (SiGe).
10. The method of claim 1 , wherein the replacement gate stack is etched by a reactive ion etching (RIE) process.
11. A method of forming a semiconductor structure, the method comprising:
depositing a dielectric over a plurality of fins;
applying a mask only over a first portion of the plurality of fins to define a second portion of the plurality of fins that are exposed by the mask including all fins to be cut;
employing the mask to remove the dielectric from the second portion of the plurality of fins including all fins to be cut;
depositing a replacement gate stack over the first and second portions of the plurality of fins;
removing the second portion of the plurality of fins including fins to be cut during etching of the replacement gate stack; and
forming a spacer within recesses formed by removal of the fins to be cut.
12. The method of claim 11 , wherein the spacer is a non-conducting dielectric layer.
13. The method of claim 11 , wherein the replacement gate stack includes a dummy gate and a gate hard mask.
14. The method of claim 13 , wherein the dummy gate is formed of amorphous silicon.
15. The method of claim 11 , wherein the mask is an organic planarization layer (OPL).
16. The method of claim 11 , wherein each of the plurality of fins is formed by silicon (Si).
17. The method of claim 11 , wherein each of the plurality of fins is formed by silicon germanium (SiGe).
18. The method of claim 11 , wherein the replacement gate stack is etched by a reactive ion etching (RIE) process.
19. The method of claim 11 , wherein the dielectric is an oxide.
20. The method of claim 19 , wherein the oxide is removed before deposition of the replacement gate stack.