Trenched gate with sidewall airgap spacer
View Patent ↗A method for fabricating a semiconductor device may include receiving a device substrate comprising a channel layer and a source or drain layer, forming a gate trench within the source or drain layer of the device substrate, depositing a gate dielectric layer and one or more additional gate layers onto the bottom and sidewalls of the gate trench, and removing a substantial portion of at least the gate dielectric layer from the sidewalls of the gate trench to form a left and a right sidewall airgap adjacent to the sidewalls of the gate trench. A corresponding semiconductor device may include a device substrate comprising a channel layer and a source or drain layer, a gate trench formed within the source or drain layer of the device substrate and a sidewall airgap formed adjacent to the sidewalls of the gate trench.
1. A method comprising:
receiving a device substrate comprising a channel layer, and a source or drain layer;
forming a gate trench within the source or drain layer of the device substrate;
depositing a gate dielectric layer onto the bottom and sidewalls of the gate trench to form a narrower and shallower trench;
depositing one or more conductive gate layers onto the bottom and sidewalls of the narrower and shallower trench; and
removing a substantial portion of at least the gate dielectric layer from the sidewalls of the gate trench to form a left and a right sidewall airgap adjacent to the sidewalls of the gate trench.
2. The method of claim 1 , wherein the one or more conductive gate layers comprise a work function layer.
3. The method of claim 1 , wherein the one or more conductive gate layers comprise a gate conductor layer.
4. The method of claim 1 , wherein forming the gate trench partitions the source or drain layer into a source and a drain.
5. The method of claim 1 , further comprising planarizing the device substrate previous to removing the gate dielectric layer from the sidewalls of the gate trench.
6. The method of claim 1 , wherein removing the gate dielectric layer from the sidewalls of the gate trench comprises conducting a low energy directional etching process.
7. The method of 1 , wherein the gate dielectric layer comprises a material selected from the group consisting of HfSiO4, ZrSiO4, HfO2, ZrO2, SiO2, HfO, ZrO, and TaO.
8. The method of claim 1 , wherein the device substrate is formed over a bulk substrate.
9. The method of claim 1 , further comprising replacing a portion of the device substrate with an isolation trench that isolates adjacent semiconductor devices.
10. The method of claim 9 , wherein the isolation trench is filled with an isolation material.