Punch through stopper in bulk finFET device
A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
1. A method for forming a semiconductor device comprising:
forming a fin structure from a bulk semiconductor substrate;
forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed;
forming a sacrificial spacer on the upper portion of the sidewall of the fin structure;
recessing the isolation region to provide an exposed section of the lower portion of the sidewall of the fin structure;
forming a doped semiconductor material on the exposed section of the fin structure, wherein the doped semiconductor material is selected from the group consisting of silicon (Si), silicon doped with carbon (Si:C), silicon germanium, silicon germanium doped with carbon (SiGe:C), germanium, gallium arsenic, indium arsenic, indium phosphide, and combinations thereof, wherein the doped semiconductor material is n-type or p-type doped;
diffusing dopant from the doped semiconductor material to a base portion of the fin structure;
removing the sacrificial spacer; and
forming source and drain regions in contact with the upper portion of the sidewall of the fin structure.
2. The method of claim 1 , further comprising forming a gate structure on a channel region portion of the fin structure after said forming the isolation region and before said forming the sacrificial spacer.
3. The method of claim 2 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after said diffusing the dopant from the doped semiconductor material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure.
4. The method of claim 3 , wherein the forming of the sacrificial spacer comprises:
conformally depositing a blanket layer of a dielectric material; and
anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure.
5. The method of claim 3 , wherein said forming the doped semiconductor material on the exposed section of the lower portion of the sidewall of the fin structure comprises epitaxial deposition of a silicon including material that is in situ doped with an n-type or p-type dopant.
6. The method of claim 1 , wherein said diffusing dopant from the doped semiconductor material to a base portion of the fin structure comprises thermal annealing selected from the group consisting of rapid thermal anneal, laser annealing and combinations thereof.
7. A method for forming a semiconductor device comprising:
forming an isolation region contacting a lower portion of a sidewall of a fin structure, wherein an upper portion of the sidewall of the fin structure is exposed;
forming a sacrificial spacer on the upper portion of the sidewall of the fin structure;
recessing the isolation region to provide an exposed section of the lower portion of the sidewall of the fin structure;
forming a doped semiconductor material on the exposed section of the fin structure, wherein the doped semiconductor material is selected from the group consisting of silicon (Si), silicon doped with carbon (Si:C), silicon germanium, silicon germanium doped with carbon (SiGe:C), germanium, gallium arsenic, indium arsenic, indium phosphide, and combinations thereof, wherein the doped semiconductor material is n-type or p-type doped; and
diffusing dopant from the doped semiconductor material to a base portion of the fin structure.
8. The method of claim 7 further comprising forming a gate structure on a channel region portion of the fin structure after said forming the isolation region and before said forming the sacrificial spacer.
9. The method of claim 8 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after said diffusing the dopant from the doped semiconductor material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure.
10. The method of claim 9 , wherein the forming of the sacrificial spacer comprises:
conformally depositing a blanket layer of a dielectric material; and
anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure.
11. The method of claim 7 , wherein said diffusing dopant from the doped semiconductor material to a base portion of the fin structure comprises thermal annealing selected from the group consisting of rapid thermal anneal, laser annealing and combinations thereof.
12. The method of claim 7 further comprising removing the sacrificial spacer.
13. The method of claim 7 further comprising forming source and drain regions in contact with the upper portion of the sidewall of the fin structure.