Fin pitch scaling for high voltage devices and low voltage devices on the same wafer
View Patent ↗A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
1. A semiconductor device comprising:
a first gate structure present on a first plurality of fin structures including a first high-k gate dielectric in contact with a channel region of the first plurality of fin structures; and
a second gate structure present on a second plurality of fin structure including a high voltage gate dielectric in contact with a channel region of the second plurality of fin structures and a second high-k gate dielectric in contact with the high-voltage dielectric,
wherein a fin upper width for fin structures in the first plurality of fin structures is greater than a fin upper width for fin structures in the second plurality of fin structures,
wherein a surface of the first plurality of fin structures and a surface of the second plurality of fin structures in contact with a substrate are coplanar, and are present in groupings of fin structures having a same pitch.
2. The semiconductor device of claim 1 , wherein the second gate structure is formed on the second plurality of fin structures without pinch off.
3. The semiconductor device of claim 1 , wherein the high voltage dielectric layer is an oxide.
4. The semiconductor device of claim 3 , wherein the high voltage dielectric layer has a thickness ranging from 3 nm to 7 nm.
5. The semiconductor device of claim 1 , a first applied voltage applied to the first gate structure is less than 1.2 eV.
6. The semiconductor device of claim 1 , wherein a second applied voltage applied to the second gate structure is greater than 2.0 eV.
7. The semiconductor device of claim 1 , wherein the fin upper width for the first plurality of fin structures has a width ranging from 5 nm to 20 nm.
8. The semiconductor device of claim 7 , wherein the fin upper width for the second plurality of fin structures has a width that is 4 nm to 6 nm less than the fin upper width for the first plurality of fin structure structures.
9. A semiconductor device comprising:
a first gate structure present on a first plurality of fin structures including a first high-k gate dielectric in contact with a channel region of the first plurality of fin structures; and
a second gate structure present on a second plurality of fin structures including a high voltage gate dielectric in contact with a channel region of the second plurality of fin structures and a second high-k gate dielectric in contact with the high-voltage dielectric, a fin upper width for fin structures in the first plurality of fin structures is greater than a fin upper width for fin structures in the second plurality of fin structures,
wherein a surface of the first plurality of fin structures and a surface of the second plurality of fin structures in contact with a substrate are coplanar, and present in groupings of fin structures having a same pitch,
wherein the first fin structure has a greater upper surface width than the second fin structure by about 4 nm to 6 nm.
10. The semiconductor device of claim 9 , wherein the second gate structure is formed on the second structure without pinch off.
11. The semiconductor device of claim 9 , wherein the high voltage dielectric layer is an oxide.
12. The semiconductor device of claim 11 , wherein the high voltage dielectric layer has a thickness ranging from 3 nm to 7 nm.
13. The semiconductor device of claim 9 , a first applied voltage applied to the first gate structure is less than 1.2 eV.
14. The semiconductor device of claim 9 , wherein a second applied voltage applied to the second gate structure is greater than 2.0 eV.
15. The semiconductor device of claim 9 , wherein the first fin structure has a width ranging from 5 nm to 20 nm.
16. The semiconductor device of claim 9 , wherein the second fin structure has a width that is 4 nm to 6 nm less than the first width.
17. A semiconductor device comprising:
a first gate structure present on a first plurality of fin structures including a first high-k gate dielectric in contact with a channel region of the first plurality of fin structures; and
a second gate structure present on a second plurality of fin structures including a high voltage gate dielectric in contact with a channel region of the second plurality of fin structures and a second high-k gate dielectric in contact with the high-voltage dielectric, the first fin structure has a greater upper width dimensions than the second fin structure,
wherein a surface of the first plurality of fin structures and a surface of the second plurality of fin structures in contact with a substrate are coplanar, and present in groupings of fin structures having a same pitch,
wherein a first applied voltage applied to the first gate structure is less than 1.2 eV, and a second applied voltage applied to the second gate structure is greater than 2.0 eV.
18. The semiconductor device of claim 17 , wherein the first fin structure and the second fin structure are present in groupings of fin structures having a same pitch.
19. The semiconductor device of claim 17 , wherein the high voltage dielectric layer has a thickness ranging from 3 nm to 7 nm.