Stable multiple threshold voltage devices on replacement metal gate CMOS devices
A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.
1. A method of forming a multiple threshold voltage transistor structure, the method comprising:
forming a first transistor having a high-k dielectric material with a first height; and
forming a second transistor having the high-k dielectric material with a second height, the first height of the high-k dielectric material being different from the second height;
wherein the first height and the second height are lengths of the high-k dielectric material extending up a sidewall trench starting at a fin underneath.
2. The method of claim 1 , wherein the first transistor has a first trench and the second transistor has a second trench.
3. The method of claim 2 , wherein the high-k dielectric material of the first transistor is in the first trench; and wherein the high-k dielectric material of the second transistor is in the second trench.
4. The method of claim 3 , wherein the first trench and the second trench are formed on the fin.
5. The method of claim 4 , wherein spacers define the first trench and the second trench.
6. The method of claim 5 , wherein a work function metal is formed on the high-k dielectric material in the first trench and the second trench.
7. The method of claim 6 , wherein a gate conduction metal is formed on the work function metal.
8. The method of claim 7 , wherein the gate conduction metal fills the first trench and the second trench.
9. The method of claim 7 , wherein an epitaxial layer is formed on the fin.
10. The method of claim 9 , wherein an interlayer dielectric layer is formed on the epitaxial layer.
11. The method of claim 10 , wherein a capping layer is on a top surface of the spacers, the interlayer dielectric layer, the work function metal, and the gate conduction metal.
12. The method of claim 2 , wherein the first trench and the second trench have a different width.
13. The method of claim 2 , wherein the first trench is narrow compared to the second trench.
14. The method of claim 1 , wherein the first height of the high-k dielectric material is less than the second height.
15. The method of claim 1 , wherein the first height of the high-k dielectric material is about half the second height.
16. The method of claim 1 , wherein the first height ranges from about 5-40 nanometers.
17. The method of claim 1 , wherein the first height is about 40 nanometers less than the second height.
18. The method of claim 1 , wherein the first height is about 60 nm less than the second height.
19. The method of claim 1 , wherein the first height of the high-k dielectric material in the first transistor forms a low threshold voltage transistor; and wherein the second height of the high-k dielectric material in the second transistor forms a high threshold voltage transistor.
20. The method of claim 1 , wherein the first height is about 20 nanometers or less shorter than the second height.