Stable multiple threshold voltage devices on replacement metal gate CMOS devices
View Patent ↗A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.
1. A method of forming a multiple threshold voltage transistor structure, the method comprising:
forming at least one narrow channel and at least one long channel on a fin, the fin being deposited on a substrate, wherein spacers on the fin define the at least one narrow channel and the at least one long channel, wherein an epitaxial layer is formed on the fin, and wherein an interlayer dielectric layer is formed on the epitaxial layer;
depositing a high-k dielectric material in the at least one narrow channel and the at least one long channel;
depositing a metal layer on the high-k dielectric material in the at least one narrow channel and the at least one long channel;
recessing a height of the high-k dielectric material in the at least one narrow channel, after performing a protective process to protect the at least one long channel;
removing the metal layer from the at least one narrow channel and the at least one long channel;
depositing a work function metal in the at least one narrow channel and the at least one long channel;
depositing a gate conduction metal to fill the at least one narrow channel and the at least one long channel; and
depositing a capping layer on a top surface of the spacers, the interlayer dielectric layer, the work function metal, and the gate conduction metal.
2. The method of claim 1 , wherein recessing the height of the high-k dielectric material in the at least one narrow channel comprises removing a top portion of the high-k dielectric material in the at least one narrow channel.
3. The method of claim 1 , wherein recessing the height of the high-k dielectric material in the at least one narrow channel comprises removing less than 20 nanometers from the height of the high-k dielectric material in the at least one narrow channel.
4. The method of claim 1 , wherein recessing the height of the high-k dielectric material in the at least one narrow channel comprises removing about 20 nanometers from the height of the high-k dielectric material in the at least one narrow channel.
5. The method of claim 1 , wherein recessing the height of the high-k dielectric material in the at least one narrow channel comprises removing about 30 nanometers from the height of the high-k dielectric material in the at least one narrow channel.
6. The method of claim 1 , wherein recessing the height of the high-k dielectric material in the at least one narrow channel comprises removing about 20-40 nanometers from the height of the high-k dielectric material in the at least one narrow channel.
7. The method of claim 1 , wherein the height of the high-k dielectric material in the at least one narrow channel is about half another height of the high-k dielectric material in the at least one long channel.
8. The method of claim 1 , wherein performing the protective process to protect the at least one long channel includes:
depositing a first protective material in the at least one narrow channel and the at least one long channel;
forming a second protective material over the first protective material above the at least one long channel;
removing a portion of the first protective material in the at least one narrow channel, while the second protective material protects the at least one long channel;
after the second protective material is removed and after recessing the height of the high-k dielectric material in the at least one narrow channel, removing the first protective material.
9. The method of claim 1 , wherein the high-k dielectric material includes hafnium oxide.
10. The method of claim 1 , wherein a recessed height of the high-k dielectric material in the at least one narrow channel forms at least one low threshold voltage transistor; and
wherein a regular height of the high-k dielectric material in the at least one long channel forms at least one high threshold voltage transistor.