III-V semiconductor devices with selective oxidation
Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.
1. A method for fabricating a semiconductor device with selective oxidation, the method comprising:
depositing a stack of two crystalline semiconductor layers over a base layer, wherein the base layer comprises a semiconductor substrate and a first insulator layer, and wherein the semiconductor substrate is 100 nanometers to 1 micrometer in thickness;
performing shallow trench isolation within the base layer to form a plurality of trenches that expose a set of sides of the two crystalline semiconductor layers;
depositing a second insulator layer into the plurality of trenches of the base layer;
selectively oxidizing a first of the two crystalline semiconductor layers to yield a selectively oxidized layer that serves as an insulator for a second of the two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers maintain a layered configuration after oxidation of the first of the two crystalline semiconductor layers;
forming a dummy gate structure, wherein a set of spacers are along sides of the dummy gate structure;
forming source and drain regions in contact with each exposed side of the set of sides of the oxidized first semiconductor layer and the second semiconductor layer of the two crystalline semiconductor layers;
depositing an insulating material;
planarizing the deposited insulator material until the dummy gate structure is exposed;
removing the dummy gate structure;
etching the selectively oxidized crystalline semiconductor layer;
forming a replacement gate layer between a plurality of walls within the set of spacers;
depositing a high-K insulator around the replacement gate layer; and
rendering a second of the two crystalline semiconductor layers as a channel region.
2. The method of claim 1 , further comprising:
performing middle of the line and back end of the line (BEOL) processes to furnish the semiconductor device.
3. The method of claim 1 , wherein the stack of two crystalline semiconductor layers comprises the first layer of the two crystalline semiconductor layers that is readily oxidized to an insulator-type material in comparison to the second layer of the two crystalline semiconductors.
4. The method of claim 1 , wherein the semiconductor substrate stack of two crystalline semiconductor layer is exposed at a temperature that is greater than or equal to 350° C. and less than or equal to 550° C.
5. The method of claim 1 , wherein the source region and the drain region are formed using an ion implantation process or epitaxy.
6. The method of claim 1 , wherein etching the selectively oxidized crystalline semiconductor layer is selective, at least in part, to the set of spacers, the channel region, and the insulating material.
7. The method of claim 1 , wherein selectively oxidizing one of the two crystalline semiconductor layers occurs after depositing the stack of two crystalline semiconductor layers over the base layer.
8. The method of claim 1 , where the set of spacers are composed of: a nitride, an oxide, or an oxynitride.