Stacked semiconductor nanowires with tunnel spacers
View Patent ↗A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material.
1. A semiconductor structure comprising:
at least one stacked semiconductor nanowire array suspended above a surface of a semiconductor substrate, wherein said at least one stacked semiconductor nanowire array includes a plurality of vertically spaced apart semiconductor nanowires;
a tunnel spacer located beneath and at end portions of each vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array, wherein a sidewall surface of each tunnel spacer is vertically coincident with a sidewall surface of each vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array;
a first gate structure located above a topmost vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array; and
a second gate structure located beneath each vertically spaced apart semiconductor nanowires of said at least one stacked semiconductor nanowire array and located between each tunnel spacer.
2. The semiconductor structure of claim 1 , further comprising a source region located on one side of the first and second gate structures and having a sidewall surface in contact with a sidewall surface of each vertically spaced apart semiconductor nanowire of said least one stacked semiconductor nanowire array, and a drain region located on another side of the first and second gate structures and having a sidewall surface in contact with a sidewall surface of each vertically spaced apart semiconductor nanowire of said least one stacked semiconductor nanowire array.
3. The semiconductor structure of claim 1 , further comprising a planarized dielectric material located above the source region and the drain region, wherein a dielectric spacer separates the planarized dielectric material located above the source region from a sidewall surface of the first gate structure, and wherein another dielectric spacer separates the planarized dielectric material located above the drain region from another sidewall surface of the first gate structure.
4. The semiconductor structure of claim 3 , wherein an upper surface of the planarized dielectric material located above both the source region and the drain region is coplanar with an upper surface of the first gate structure.
5. The semiconductor structure of claim 1 , wherein said first gate structure comprises a U-shaped gate dielectric having a bottommost portion in direct contact with an upper surface of the topmost vertically spaced apart semiconductor nanowire and a gate conductor located on the U-shaped gate dielectric.
6. The semiconductor structure of claim 5 , wherein said U-shaped gate dielectric comprises a dielectric material having a dielectric constant of greater than silicon oxide.
7. The semiconductor structure of claim 1 , wherein said second gate structure comprises a gate dielectric that surrounds a gate conductor.
8. The semiconductor structure of claim 7 , wherein said gate dielectric comprises a dielectric material having a dielectric constant of greater than silicon oxide.
9. The semiconductor structure of claim 7 , wherein a sidewall portion of the gate dielectric of each second gate structure contacts a sidewall surface of each tunnel spacer.
10. The semiconductor structure of claim 1 , wherein each vertically spaced apart semiconductor nanowire comprises single crystal silicon.