Stacked nanowire devices
View Patent ↗A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
1. A semiconductor device comprising:
a first stack of nanowires arranged on a substrate comprising a first nanowire and a second nanowire, the first nanowire and the second nanowire arranged substantially parallel with the substrate;
a second stack of nanowires arranged on the substrate comprising a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially parallel with the substrate, the third nanowire arranged substantially co-planar in a first plane with the first nanowire, the fourth nanowire arranged substantially co-planar in a second plane with the second nanowire; and
the first nanowire and the second nanowire comprising a first semiconductor material and the third nanowire and the fourth nanowire comprising a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
2. The device of claim 1 , wherein the first semiconductor material includes silicon.
3. The device of claim 1 , wherein the second semiconductor material includes silicon germanium.
4. The device of claim 1 , further comprising a first gate stack arranged over a channel region of the first stack of nanowires.
5. The device of claim 4 , further comprising spacers arranged adjacent to the first gate stack.
6. The device of claim 5 , further comprising a source/drain region arranged adjacent to the spacers.
7. The device of claim 6 wherein the first nanowire extends through the spacer and into the source/drain region.
8. The device of claim 1 , further comprising a second gate stack arranged over a channel region of the second stack of nanowires.
9. The device of claim 8 , further comprising spacers arranged adjacent to the second gate stack.
10. The device of claim 9 , further comprising a source/drain region arranged adjacent to the spacers.
11. A semiconductor device comprising:
a first stack of nanowires arranged on a substrate comprising a first nanowire vertically stacked over a second nanowire;
a second stack of nanowires arranged on the substrate comprising a third nanowire vertically stacked over a fourth nanowire, the third nanowire arranged substantially co-planar in a first plane with the first nanowire, the first plane substantially parallel to a surface of the substrate; and
the first nanowire and the second nanowire comprising a first semiconductor material and the third nanowire and the fourth nanowire comprising a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
12. The device of claim 11 , wherein the first semiconductor material includes silicon.
13. The device of claim 11 , wherein the second semiconductor material includes silicon germanium.
14. The device of claim 11 , further comprising a first gate stack arranged over a channel region of the first nanowire and a channel region of the second nanowire.
15. The device of claim 14 , further comprising spacers arranged adjacent to the first gate stack.
16. The device of claim 15 , further comprising a source/drain region arranged adjacent to the spacers.
17. The device of claim 16 , wherein the first nanowire extends through the spacer and into the source/drain region.
18. The device of claim 14 , further comprising a second gate stack arranged over a channel region of the second stack of nanowires.