Fin pitch scaling for high voltage devices and low voltage devices on the same wafer
View Patent ↗A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
1. A semiconductor device comprising:
a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width;
a first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor; and
a second gate structure is formed on the second plurality of fin structures including an high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
2. The semiconductor device of claim 1 , wherein the first plurality of fin structures and the second plurality of fin structures have substantially a same pitch.
3. The semiconductor device of claim 1 , wherein the second gate structure is formed on the second plurality of fin structures without pinch off.
4. The semiconductor device of claim 1 , wherein the high voltage dielectric layer is an oxide.
5. The semiconductor device of claim 4 , wherein the high voltage dielectric layer has a thickness ranging from 3 nm to 7 nm.
6. The semiconductor device of claim 1 , a first applied voltage applied to the first gate structure is less than 1.2 eV, and a second applied voltage applied to the second gate structure is greater than 2.0 eV.
7. The semiconductor device of claim 1 , wherein at least one of the first and second high-k gate dielectric layer is a composition selected from the group consisting of HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and combinations thereof.
8. The semiconductor device of claim 1 , wherein the first width ranges from 5 nm to 20 nm.
9. The semiconductor device of claim 8 , wherein the second width is 4 nm to 6 nm less than the first width.
10. A semiconductor device comprising:
a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being 4 nm to 6 nm less than the first width;
a first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor; and
a second gate structure is formed on the second plurality of fin structures including an high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
11. The semiconductor device of claim 10 , wherein the first plurality of fin structures and the second plurality of fin structures have substantially a same pitch.
12. The semiconductor device of claim 10 , wherein the second gate structure is formed on the second plurality of fin structures without pinch off.
13. The semiconductor device of claim 10 , wherein the high voltage dielectric layer is an oxide.
14. The semiconductor device of claim 13 , wherein the high voltage dielectric layer has a thickness ranging from 3 nm to 7 nm.
15. The semiconductor device of claim 10 , a first applied voltage applied to the first gate structure is less than 1.2 eV, and a second applied voltage applied to the second gate structure is greater than 2.0 eV.
16. The semiconductor device of claim 10 , wherein at least one of the first and second high-k gate dielectric layer is a composition selected from the group consisting of HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and combinations thereof.
17. The semiconductor device of claim 10 , wherein the first width ranges from 5 nm to 20 nm.
18. A semiconductor device comprising:
a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being 4 nm to 6 nm less than the first width;
a first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor; and
a second gate structure is formed on the second plurality of fin structures including an high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor, wherein 1 first applied voltage applied to the first gate structure is less than 1.2 eV, and a second applied voltage applied to the second gate structure is greater than 2.0 eV.
19. The semiconductor device of claim 18 , wherein the first plurality of fin structures and the second plurality of fin structures have substantially a same pitch.
20. The semiconductor device of claim 18 , wherein the high voltage dielectric layer has a thickness ranging from 3 nm to 7 nm.