Fully aligned via with integrated air gaps
View Patent ↗A wafer is provided. The wafer includes a dielectric layer, first and second metallization layer interconnects arrayed across the dielectric layer with the second metallization layer interconnects adjacent one another and surrounded by the first metallization layer interconnects and a cap. The first and second metallization layer interconnects have respective upper surfaces defining a first plane and a second plane recessed from the first plane, respectively. The cap is disposed on exposed surfaces of the second metallization layer interconnects and portions of the dielectric layer adjacent to the second metallization layer interconnects.
1. A processing method for a wafer comprising central, lateral and outer metallization layer interconnects arrayed across a dielectric layer, the processing method comprising:
using a single mask exposure to recess only the central and lateral metallization layer interconnects;
forming air gaps in a secondary dielectric layer in defined air gap regions adjacent to the outer metallization layer interconnects; and
forming a fully-aligned via (FAV) through at least the secondary dielectric for electrical communication with the central metallization layer interconnect.
2. The processing method according to claim 1 , wherein using the single mask exposure comprises depositing a lithographic layer with an air gap mask.
3. The processing method according to claim 1 , wherein forming the air gaps in the secondary dielectric comprises non-conformal deposition of the secondary dielectric.
4. The processing method according to claim 1 , wherein the central, lateral and outer metallization layer interconnects and the FAV each comprise:
a metallic material; and
a lining at least partially surrounding the metallic material, wherein:
the lining comprises an interior lining of a first material and an exterior lining of a second material,
the first material comprises one of tantalum (Ta) or tantalum nitride (TaN), and
the second material comprises one of cobalt (Co), ruthenium (Ru) or Ta.
5. The processing method according to claim 1 , wherein the secondary dielectric layer has curved and tapered surfaces at the air gaps.
6. The processing method according to claim 1 further comprising forming a metallization layer over a remainder of the secondary dielectric layer and electrically coupling the FAV with the metallization layer.
7. A processing method for a wafer comprising central, lateral and outer metallization layer interconnects arrayed across a dielectric layer, the processing method comprising:
recessing the central and lateral metallization layer interconnects;
forming a protective cap over the recessed central and lateral metallization layer interconnects;
defining air gap regions adjacent to the outer metallization layer interconnects in the dielectric layer;
forming a secondary cap on exposed surfaces of the lateral and outer metallization layer interconnects, the dielectric layer and the protective cap;
non-conformally depositing a secondary dielectric layer over the secondary cap to form air gaps in the air gap regions;
defining a trench extending through the secondary dielectric layer, the secondary cap and the protective cap to the central metallization layer interconnect; and
forming a fully-aligned via (FAV) in the trench for electrical communication with the central metallization layer interconnect.
8. The processing method according to claim 7 , wherein recessing the central and lateral metallization layer interconnects comprises using a single mask exposure through deposition of a lithographic layer with an air gap mask.
9. The processing method according to claim 7 , wherein the central, lateral and outer metallization layer interconnects and the FAV each comprise:
a metallic material; and
a lining at least partially surrounding the metallic material, wherein:
the lining comprises an interior lining of a first material and an exterior lining of a second material,
the first material comprises one of tantalum (Ta) or tantalum nitride (TaN), and
the second material comprises one of cobalt (Co), ruthenium (Ru) or Ta.
10. The processing method according to claim 7 , wherein the protective cap and the secondary cap comprise silicon carbon nitride (SiCN).
11. The processing method according to claim 7 , wherein the secondary dielectric layer has curved and tapered surfaces at the air gaps.
12. The processing method according to claim 7 further comprising forming a metallization layer over a remainder of the secondary dielectric layer and electrically coupling the FAV with the metallization layer.