Forming a hybrid channel nanosheet semiconductor structure
View Patent ↗A nanosheet semiconductor structure includes a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having second inner spacer comprised of a second material. The first material is different than the second material.
1. A nanosheet semiconductor structure comprising:
a first nanosheet field effect transistor (FET) structure comprising a first silicon germanium (SiGe) channel comprised in a first channel region of a first FET region, wherein the first SiGe channel comprises one or more SiGe nanosheets, and wherein a first inner spacer comprised of a first material is comprised in the first channel region; and
a second nanosheet FET structure comprising a second SiGe channel comprised in a second channel region of a second FET region, wherein the second SiGe channel comprises one or more SiGe nanosheets, and wherein a second inner spacer comprised of a second material is comprised in the second channel region;
wherein the first material is different than the second material.
2. The structure of claim 1 , wherein the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure.
3. The structure of claim 1 , wherein the first FET structure further comprises:
a first substrate;
wherein the first SiGe channel region is formed on the first substrate and comprises the first SiGe channel and a first work function metal; and
a first gate comprising a first metal.
4. The structure of claim 3 , wherein the first substrate is comprised of Si.
5. The structure of claim 3 , wherein the first SiGe channel region further comprises a first source/drain region.
6. The structure of claim 3 , wherein the first metal is comprised of tungsten (W).
7. The structure of claim 1 , wherein the second FET structure further comprises:
a second substrate;
wherein the second SiGe channel region is formed on the second substrate and comprises the second SiGe channel; and
a second gate comprising a second metal.
8. The structure of claim 7 , wherein the second substrate is comprised of Si.
9. The structure of claim 7 , wherein the second SiGe channel region further comprises a second source/drain region.
10. The structure of claim 7 , wherein the second metal is comprised of tungsten (W).
11. An integrated circuit comprising:
a first nanosheet field effect transistor (FET) structure comprising a first SiGe channel comprised in a first channel region of a first FET region, wherein the first SiGe channel comprises one or more SiGe nanosheets, and wherein a first inner spacer comprised of a first material is comprised in the first channel region; and
a second nanosheet FET structure comprising a second SiGe channel comprised in a second channel region of a second FET region, wherein the second SiGe channel comprises one or more SiGe nanosheets, and wherein a second inner spacer comprised of a second material is comprised in the second channel region;
wherein the first material is different than the second material.
12. The integrated circuit of claim 11 , wherein the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure.
13. The integrated circuit of claim 11 , wherein the first FET structure further comprises:
a first substrate;
wherein the first SiGe channel region is formed on the first substrate and comprises the first SiGe channel and a first work function metal; and
a first gate comprising a first metal.
14. The integrated circuit of claim 13 , wherein the first substrate is comprised of Si.
15. The integrated circuit of claim 13 , wherein the first SiGe channel region further comprises a first source/drain region.
16. The integrated circuit of claim 13 , wherein the first metal is comprised of tungsten (W).
17. The integrated circuit of claim 13 , wherein the second FET structure further comprises:
a second substrate;
wherein the second SiGe channel region is formed on the second substrate and comprises the second SiGe channel; and
a second gate comprising a second metal.
18. The integrated circuit of claim 17 , wherein the second substrate is comprised of Si.
19. The integrated circuit of claim 17 , wherein the second SiGe channel region further comprises a second source/drain region.
20. The integrated circuit of claim 17 , wherein the second metal is comprised of tungsten (W).