Transistor with air spacer and self-aligned contact
View Patent ↗A method of fabricating a semiconductor transistor and the semiconductor transistor include a source region and a drain region within a substrate. The method includes forming a gate above the substrate, forming a source contact above the source region and a drain contact above the drain region, and forming air spacers within a dielectric between the gate and each of the source contact and the drain contact. Metal caps are formed on the source contact and the drain contact, and a gate cap is formed between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact.
1. A method of fabricating a semiconductor transistor, the method comprising:
forming a source region and a drain region within a substrate;
forming a gate above the substrate;
forming a source contact above the source region and a drain contact above the drain region;
forming air spacers within a dielectric between the gate and each of the source contact and the drain contact;
forming metal caps on the source contact and the drain contact;
forming a gate cap between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact;
forming an inter-layer dielectric (ILD) above the source region and the drain region; and
forming sacrificial spacers between the gate and the ILD and a sacrificial cap above the gate, wherein the air spacers include a seam within the dielectric in the space left by the removing the sacrificial cap.
2. The method according to claim 1 , wherein the forming the gate includes forming a high-k dielectric liner for the gate, the high-k dielectric liner being adjacent to the dielectric within which the air spacers are formed.
3. The method according to claim 1 , wherein the forming the source contact and the drain contact includes removing the sacrificial spacers and the sacrificial cap and forming trenches in the ILD.
4. The method according to claim 3 , further comprising forming the dielectric in the spaces left by the removing the sacrificial spacers and the sacrificial cap.
5. The method according to claim 1 , wherein the forming the metal caps includes selectively forming the metal caps only above the source contact and the drain contact.
6. The method according to claim 1 , wherein the forming the gate cap includes disposing the gate cap between the selective metal caps as a void-free layer.
7. The method according to claim 1 , wherein the forming the gate cap includes conformally depositing the gate cap on the selective metal caps and the dielectric and planarizing the gate cap to be level with the selective metal caps.
8. The method according to claim 7 , wherein the conformally depositing the gate cap includes depositing silicon oxygen carbon (SiOC).
9. The method according to claim 1 , further comprising forming a higher-level inter layer dielectric (ILD) layer above the selective metal caps and the gate cap.
10. The method according to claim 9 , further comprising patterning trenches for the higher-level contacts within the higher-level ILD layer.
11. The method according to claim 10 , wherein the patterning the trenches includes forming the trenches above the metal caps and portions of the gate cap adjacent to the metal caps.
12. The method according to claim 10 , further comprising over-etching into the portions of the gate cap during the patterning the trenches, wherein a layer of the gate cap remains under the portion of the bottom surface of the higher-level contacts.